AES-based cryptographic and biometric security coprocessor IC in 0.18-μ;m CMOS resistant to side-channel power analysis attacks

Kris Tiri; David D. Hwang; Alireza Hodjat; Bo-Cheng Lai; Shenglin Yang; Patrick Schaumont; Ingrid Verbauwhede

doi:10.1109/VLSIC.2005.1469370

AES-based cryptographic and biometric security coprocessor IC in 0.18-μ;m CMOS resistant to side-channel power analysis attacks

Kris Tiri^*, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

27 Scopus citations

Abstract

This paper describes an embedded security coprocessor that consists of four components: an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical coprocessors are fabricated using a TSMC 6M 0.18-μm process. The first coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second coprocessor uses Wave Dynamic Differential Logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The coprocessor is part of a security-partitioned embedded system called ThumbPod.

Original language	English
Title of host publication	2005 Symposium on VLSI Circuits - Digest of Technical Papers
Pages	216-219
Number of pages	4
DOIs	https://doi.org/10.1109/VLSIC.2005.1469370
State	Published - 2005
Event	2005 Symposium on VLSI Circuits - Kyoto, Japan Duration: 16 Jun 2005 → 18 Jun 2005

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2005

Conference

Conference	2005 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	16/06/05 → 18/06/05

Keywords

Advanced Encryption Standard (AES)
Biometrics
Coprocessor
Cryptography
Differential power analysis

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10.1109/VLSIC.2005.1469370

Cite this

Tiri, K., Hwang, D. D., Hodjat, A., Lai, B.-C., Yang, S., Schaumont, P., & Verbauwhede, I. (2005). AES-based cryptographic and biometric security coprocessor IC in 0.18-μ;m CMOS resistant to side-channel power analysis attacks. In 2005 Symposium on VLSI Circuits - Digest of Technical Papers (pp. 216-219). Article 1469370 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2005). https://doi.org/10.1109/VLSIC.2005.1469370

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abstract = "This paper describes an embedded security coprocessor that consists of four components: an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical coprocessors are fabricated using a TSMC 6M 0.18-μm process. The first coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second coprocessor uses Wave Dynamic Differential Logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The coprocessor is part of a security-partitioned embedded system called ThumbPod.",

keywords = "Advanced Encryption Standard (AES), Biometrics, Coprocessor, Cryptography, Differential power analysis",

author = "Kris Tiri and Hwang, {David D.} and Alireza Hodjat and Bo-Cheng Lai and Shenglin Yang and Patrick Schaumont and Ingrid Verbauwhede",

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series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

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Tiri, K, Hwang, DD, Hodjat, A, Lai, B-C, Yang, S, Schaumont, P & Verbauwhede, I 2005, AES-based cryptographic and biometric security coprocessor IC in 0.18-μ;m CMOS resistant to side-channel power analysis attacks. in 2005 Symposium on VLSI Circuits - Digest of Technical Papers., 1469370, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2005, pp. 216-219, 2005 Symposium on VLSI Circuits, Kyoto, Japan, 16/06/05. https://doi.org/10.1109/VLSIC.2005.1469370

AES-based cryptographic and biometric security coprocessor IC in 0.18-μ;m CMOS resistant to side-channel power analysis attacks. / Tiri, Kris; Hwang, David D.; Hodjat, Alireza et al.
2005 Symposium on VLSI Circuits - Digest of Technical Papers. 2005. p. 216-219 1469370 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Tiri K, Hwang DD, Hodjat A, Lai BC, Yang S, Schaumont P et al. AES-based cryptographic and biometric security coprocessor IC in 0.18-μ;m CMOS resistant to side-channel power analysis attacks. In 2005 Symposium on VLSI Circuits - Digest of Technical Papers. 2005. p. 216-219. 1469370. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2005.1469370

AES-based cryptographic and biometric security coprocessor IC in 0.18-μ;m CMOS resistant to side-channel power analysis attacks

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