Advanced layout design for deep-submicron CMOS output buffer with higher driving capability and better ESD reliability

Ming-Dou Ker; Chung-Yu Wu; Tung Yang Chen

doi:10.1109/VTSA.1997.614724

Advanced layout design for deep-submicron CMOS output buffer with higher driving capability and better ESD reliability

Ming-Dou Ker^*, Chung-Yu Wu, Tung Yang Chen

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

Abstract

Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.

Original language	English
Pages	45-49
Number of pages	5
DOIs	https://doi.org/10.1109/VTSA.1997.614724
State	Published - 1997
Event	Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China Duration: 3 Jun 1997 → 5 Jun 1997

Conference

Conference	Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
City	Taipei, China
Period	3/06/97 → 5/06/97

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10.1109/VTSA.1997.614724

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title = "Advanced layout design for deep-submicron CMOS output buffer with higher driving capability and better ESD reliability",

abstract = "Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.",

author = "Ming-Dou Ker and Chung-Yu Wu and Chen, {Tung Yang}",

year = "1997",

doi = "10.1109/VTSA.1997.614724",

language = "English",

pages = "45--49",

note = "Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications ; Conference date: 03-06-1997 Through 05-06-1997",

}

Advanced layout design for deep-submicron CMOS output buffer with higher driving capability and better ESD reliability. / Ker, Ming-Dou; Wu, Chung-Yu; Chen, Tung Yang.
1997. 45-49 Paper presented at Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, Taipei, China.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Advanced layout design for deep-submicron CMOS output buffer with higher driving capability and better ESD reliability

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Chen, Tung Yang

PY - 1997

Y1 - 1997

N2 - Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.

AB - Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.

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DO - 10.1109/VTSA.1997.614724

M3 - Paper

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T2 - Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications

Y2 - 3 June 1997 through 5 June 1997

ER -

Advanced layout design for deep-submicron CMOS output buffer with higher driving capability and better ESD reliability

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