Advanced bipolar technology for the 1990s

J. Y.C. Sun, J. H. Comfort, J. Warnock, J. D. Cressler, G. Patton, J. M.C. Stork, J. Burghartz, D. Harame, E. Crabbe, P. F. Lu, M. Arienzo, B. Meyerson

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The advent of low temperature epitaxy processes provides a new degree of freedom for bipolar device scaling. This paper describes new vertical scaling concepts and process technology elements required for advanced scaled bipolar (NPN and PNP) devices which will be the core of high-performance application-specific bipolar, BiCMOS, or complementary bipolar/BiCMOS logic and memory chips. In particular, the authors address key issues such as transit time reduction by SiGe base band-gap engineering, junction field/capacitance control by using lightly-doped emitter (LDE) and collector (LDC) concepts, lateral scaling (reduction of parasitic R and C) by advanced self-aligned structures and trench isolations, and liquid-nitrogen temperature (LNT) operation. Challenges for future BiCMOS and complementary bipolar/BiCMOS process technologies are examined.

Original languageEnglish
Title of host publication1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers, VTSA 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages269-273
Number of pages5
ISBN (Electronic)078030036X, 9780780300361
DOIs
StatePublished - 1991
Event1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991 - Taipei, Taiwan
Duration: 22 May 199124 May 1991

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)1930-8868

Conference

Conference1991 International Symposium on VLSI Technology, Systems, and Applications, VTSA 1991
Country/TerritoryTaiwan
CityTaipei
Period22/05/9124/05/91

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