Active ESD protection for input transistors in a 40-nm CMOS process

Federico A. Altolaguirre; Ming-Dou Ker

doi:10.1109/VLSI-DAT.2015.7114533

Active ESD protection for input transistors in a 40-nm CMOS process

Federico A. Altolaguirre, Ming-Dou Ker

Institute of Lighting and Energy Photonics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.

Original language	English
Title of host publication	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479962754
DOIs	https://doi.org/10.1109/VLSI-DAT.2015.7114533
State	Published - 28 May 2015
Event	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan Duration: 27 Apr 2015 → 29 Apr 2015

Publication series

Name	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Country/Territory	Taiwan
City	Hsinchu
Period	27/04/15 → 29/04/15

Keywords

CMOS ICs
ESD
ESD protection
Reliability

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10.1109/VLSI-DAT.2015.7114533

Cite this

Altolaguirre, F. A., & Ker, M-D. (2015). Active ESD protection for input transistors in a 40-nm CMOS process. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 [7114533] (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2015.7114533

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title = "Active ESD protection for input transistors in a 40-nm CMOS process",

abstract = "This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.",

keywords = "CMOS ICs, ESD, ESD protection, Reliability",

author = "Altolaguirre, {Federico A.} and Ming-Dou Ker",

year = "2015",

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Altolaguirre, FA & Ker, M-D 2015, Active ESD protection for input transistors in a 40-nm CMOS process. in 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015., 7114533, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, 27/04/15. https://doi.org/10.1109/VLSI-DAT.2015.7114533

Active ESD protection for input transistors in a 40-nm CMOS process. / Altolaguirre, Federico A.; Ker, Ming-Dou.

2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7114533 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Active ESD protection for input transistors in a 40-nm CMOS process

AU - Altolaguirre, Federico A.

AU - Ker, Ming-Dou

PY - 2015/5/28

Y1 - 2015/5/28

N2 - This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.

AB - This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.

KW - CMOS ICs

KW - ESD

KW - ESD protection

KW - Reliability

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DO - 10.1109/VLSI-DAT.2015.7114533

M3 - Conference contribution

AN - SCOPUS:84936972745

T3 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

BT - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 27 April 2015 through 29 April 2015

ER -

Active ESD protection for input transistors in a 40-nm CMOS process

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Keywords

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