Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

Shih Hung Chen; Ming-Dou Ker

doi:10.1016/j.microrel.2007.07.095

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

Shih Hung Chen^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness.

Original language	English
Pages (from-to)	1502-1505
Number of pages	4
Journal	Microelectronics Reliability
Volume	47
Issue number	9-11 SPEC. ISS.
DOIs	https://doi.org/10.1016/j.microrel.2007.07.095
State	Published - 1 Aug 2007

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10.1016/j.microrel.2007.07.095

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title = "Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits",

abstract = "CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness.",

author = "Chen, {Shih Hung} and Ming-Dou Ker",

year = "2007",

month = aug,

day = "1",

doi = "10.1016/j.microrel.2007.07.095",

language = "English",

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journal = "Microelectronics and Reliability",

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publisher = "Elsevier Limited",

number = "9-11 SPEC. ISS.",

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T1 - Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

AU - Chen, Shih Hung

AU - Ker, Ming-Dou

PY - 2007/8/1

Y1 - 2007/8/1

N2 - CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness.

AB - CDM ESD event has become the main ESD reliability concern for integrated-circuits products using nanoscale CMOS technology. A novel CDM ESD protection design, using self-biased current trigger (SBCT) and source pumping, has been proposed and successfully verified in 0.13-μm CMOS technology to achieve 1-kV CDM ESD robustness.

UR - http://www.scopus.com/inward/record.url?scp=34548681876&partnerID=8YFLogxK

U2 - 10.1016/j.microrel.2007.07.095

DO - 10.1016/j.microrel.2007.07.095

M3 - Article

AN - SCOPUS:34548681876

SN - 0026-2714

VL - 47

SP - 1502

EP - 1505

JO - Microelectronics and Reliability

JF - Microelectronics and Reliability

IS - 9-11 SPEC. ISS.

ER -

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

Abstract

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