A World First QLC RRAM: Highly Reliable Resistive-Gate Flash with Record 108Endurance and Excellent Retention

M. Y. Li, J. P. Lee, C. H. Liu, J. C. Guo, Steve S. Chung*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we demonstrated successfully a quad-level cell (QLC) of a resistive-gate memory. It was implemented in a 1k bits chip with integration of FinFET core on a mature logic platform. Comprehensive reliabilities have been examined. The results show the forming-free property, low programming current (< μ A), high endurance and excellent data retention. A record high 5×108 endurance can be achieved. Furthermore, a 4-bit-per-cell (16 levels) has been demonstrated successfully. The chip-level performance is also analyzed, showing well disturbance-immune during SET/RESET, READ, which kept healthy signal-to-noise margin, 2-3x. This architecture is a strong candidate for the next generation resistance memory.

Original languageEnglish
Title of host publication2023 IEEE International Reliability Physics Symposium, IRPS 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665456722
DOIs
StatePublished - 2023
Event61st IEEE International Reliability Physics Symposium, IRPS 2023 - Monterey, United States
Duration: 26 Mar 202330 Mar 2023

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
Volume2023-March
ISSN (Print)1541-7026

Conference

Conference61st IEEE International Reliability Physics Symposium, IRPS 2023
Country/TerritoryUnited States
CityMonterey
Period26/03/2330/03/23

Keywords

  • FinFET
  • Quad-level Cell (QLC)
  • Reliability
  • Resistance memory
  • RG-Flash
  • RRAM

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