A versatile multimedia functional unit design using the spurious power suppression technique

Kuan Hung Chen; Yu Min Chen; Yuan Sun Chu; Jiun-In  Guo

doi:10.1109/ASSCC.2006.357864

A versatile multimedia functional unit design using the spurious power suppression technique

Kuan Hung Chen^*, Yu Min Chen, Yuan Sun Chu, Jiun-In Guo

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

14 Scopus citations

Abstract

This paper presents a Versatile Multimedia Functional Unit (VMFU) which can compute six arithmetic operations, i.e. addition, subtraction, multiplication, MAC, interpolation, and SAD with different configurations. The VMFU is constructed on the basis of a row-based modified Booth encoding multiplier which consumes the lowest power among others according to our transistor-level simulations. Besides, we apply the Spurious Power Suppression Technique (SPST) to the proposed VMFU to decrease the wasted dynamic power dissipation. From the transistor-level simulations, the proposed VMFU dissipates 0.0142 mW/MHz under a 0.18um/1.8V CMOS technology. Adopting the SPST can reduce 24% power consumption with only a 15% area overhead.

Original language	English
Pages	111-114
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357864
State	Published - 2006
Event	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 13 Nov 2006 → 15 Nov 2006

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
Country/Territory	China
City	Hangzhou
Period	13/11/06 → 15/11/06

Keywords

Low-power
Multimedia
VLSI design
Versatile

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10.1109/ASSCC.2006.357864

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@conference{7b9485bfeb8d468b81fec51b249af59b,

title = "A versatile multimedia functional unit design using the spurious power suppression technique",

abstract = "This paper presents a Versatile Multimedia Functional Unit (VMFU) which can compute six arithmetic operations, i.e. addition, subtraction, multiplication, MAC, interpolation, and SAD with different configurations. The VMFU is constructed on the basis of a row-based modified Booth encoding multiplier which consumes the lowest power among others according to our transistor-level simulations. Besides, we apply the Spurious Power Suppression Technique (SPST) to the proposed VMFU to decrease the wasted dynamic power dissipation. From the transistor-level simulations, the proposed VMFU dissipates 0.0142 mW/MHz under a 0.18um/1.8V CMOS technology. Adopting the SPST can reduce 24% power consumption with only a 15% area overhead.",

keywords = "Low-power, Multimedia, VLSI design, Versatile",

author = "Chen, {Kuan Hung} and Chen, {Yu Min} and Chu, {Yuan Sun} and Jiun-In Guo",

year = "2006",

doi = "10.1109/ASSCC.2006.357864",

language = "English",

pages = "111--114",

note = "2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 ; Conference date: 13-11-2006 Through 15-11-2006",

}

TY - CONF

T1 - A versatile multimedia functional unit design using the spurious power suppression technique

AU - Chen, Kuan Hung

AU - Chen, Yu Min

AU - Chu, Yuan Sun

AU - Guo, Jiun-In

PY - 2006

Y1 - 2006

N2 - This paper presents a Versatile Multimedia Functional Unit (VMFU) which can compute six arithmetic operations, i.e. addition, subtraction, multiplication, MAC, interpolation, and SAD with different configurations. The VMFU is constructed on the basis of a row-based modified Booth encoding multiplier which consumes the lowest power among others according to our transistor-level simulations. Besides, we apply the Spurious Power Suppression Technique (SPST) to the proposed VMFU to decrease the wasted dynamic power dissipation. From the transistor-level simulations, the proposed VMFU dissipates 0.0142 mW/MHz under a 0.18um/1.8V CMOS technology. Adopting the SPST can reduce 24% power consumption with only a 15% area overhead.

AB - This paper presents a Versatile Multimedia Functional Unit (VMFU) which can compute six arithmetic operations, i.e. addition, subtraction, multiplication, MAC, interpolation, and SAD with different configurations. The VMFU is constructed on the basis of a row-based modified Booth encoding multiplier which consumes the lowest power among others according to our transistor-level simulations. Besides, we apply the Spurious Power Suppression Technique (SPST) to the proposed VMFU to decrease the wasted dynamic power dissipation. From the transistor-level simulations, the proposed VMFU dissipates 0.0142 mW/MHz under a 0.18um/1.8V CMOS technology. Adopting the SPST can reduce 24% power consumption with only a 15% area overhead.

KW - Low-power

KW - Multimedia

KW - VLSI design

KW - Versatile

UR - http://www.scopus.com/inward/record.url?scp=34250834462&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2006.357864

DO - 10.1109/ASSCC.2006.357864

M3 - Paper

AN - SCOPUS:34250834462

SP - 111

EP - 114

T2 - 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006

Y2 - 13 November 2006 through 15 November 2006

ER -

A versatile multimedia functional unit design using the spurious power suppression technique

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Keywords

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