TY - JOUR
T1 - A Variation-Tolerant Subthreshold to Superthreshold Level Shifter for Heterogeneous Interfaces
AU - Ho, Yingchieh
AU - Hsu, Shu Yu
AU - Lee, Chen-Yi
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2016/2
Y1 - 2016/2
N2 - This brief presents a subthreshold to superthreshold level shifter (LS) for linking heterogeneous interfaces. As conventional LSs convert subthreshold signals to superthreshold ones, different device characteristics result in an imbalance of driving capability. However, process and temperature variations make the yield of LS much worse. With the proposed bootstrapping technique, this work not only eliminates tremendous imbalance of MOS driving capability but also reduces degradation due to process and temperature variations. According to Monte Carlo simulations, our design shows high concentration to driving current, delay time, and duty cycle. The delay variation coefficient is only 14%. Implemented in a 65-nm CMOS SPRVT process, the measured results show that our proposal shifts the voltage level from 0.2 to 1.0 V with an average of 12.9 ns delay time at 5 MHz. In addition, the measured delay time and duty cycle have high concentration even when temperature varies from-20 °C to 120 °C.
AB - This brief presents a subthreshold to superthreshold level shifter (LS) for linking heterogeneous interfaces. As conventional LSs convert subthreshold signals to superthreshold ones, different device characteristics result in an imbalance of driving capability. However, process and temperature variations make the yield of LS much worse. With the proposed bootstrapping technique, this work not only eliminates tremendous imbalance of MOS driving capability but also reduces degradation due to process and temperature variations. According to Monte Carlo simulations, our design shows high concentration to driving current, delay time, and duty cycle. The delay variation coefficient is only 14%. Implemented in a 65-nm CMOS SPRVT process, the measured results show that our proposal shifts the voltage level from 0.2 to 1.0 V with an average of 12.9 ns delay time at 5 MHz. In addition, the measured delay time and duty cycle have high concentration even when temperature varies from-20 °C to 120 °C.
KW - Heterogeneous interfaces
KW - bootstrapped circuit
KW - energy efficient
KW - level shifter
KW - sub-Threshold circuit
UR - http://www.scopus.com/inward/record.url?scp=84962252449&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2015.2415714
DO - 10.1109/TCSII.2015.2415714
M3 - Article
AN - SCOPUS:84962252449
SN - 1549-7747
VL - 63
SP - 161
EP - 165
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 2
M1 - 7065309
ER -