A Unique Approach to Generate Self-Aligned SiO₂/Ge/SiO₂/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step

We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO₂/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO₂ layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our “designer” heterostructure are evidenced by the low interface trap density of as low as 2–4 × 10¹¹ cm⁻² eV⁻¹ and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO₂ layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO₂/SiGe channel MOSFETs.