A unified processor architecture for RISC & VLIW DSP

Tay Jyi Lin; Chie Min Chao; Chia Hsien Liu; Pi Chen Hsiao; Shin Kai Chen; Li Chun Lin; Chih-Wei Liu; Chein Wei Jen

doi:10.1145/1057661.1057675

A unified processor architecture for RISC & VLIW DSP

Tay Jyi Lin^*, Chie Min Chao, Chia Hsien Liu, Pi Chen Hsiao, Shin Kai Chen, Li Chun Lin, Chih-Wei Liu, Chein Wei Jen

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

10 Scopus citations

Abstract

This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mm ×3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power.

Original language	English
Pages	50-55
Number of pages	6
DOIs	https://doi.org/10.1145/1057661.1057675
State	Published - Apr 2005
Event	2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States Duration: 17 Apr 2005 → 19 Apr 2005

Conference

Conference	2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
Country/Territory	United States
City	Chicago, IL
Period	17/04/05 → 19/04/05

Keywords

Digital signal processor
Dual-core processor
Register organization
Variable-length instruction encoding

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10.1145/1057661.1057675

Cite this

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title = "A unified processor architecture for RISC & VLIW DSP",

abstract = "This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mm ×3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power.",

keywords = "Digital signal processor, Dual-core processor, Register organization, Variable-length instruction encoding",

author = "Lin, {Tay Jyi} and Chao, {Chie Min} and Liu, {Chia Hsien} and Hsiao, {Pi Chen} and Chen, {Shin Kai} and Lin, {Li Chun} and Chih-Wei Liu and Jen, {Chein Wei}",

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doi = "10.1145/1057661.1057675",

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AU - Lin, Tay Jyi

AU - Chao, Chie Min

AU - Liu, Chia Hsien

AU - Hsiao, Pi Chen

AU - Chen, Shin Kai

AU - Lin, Li Chun

AU - Liu, Chih-Wei

AU - Jen, Chein Wei

PY - 2005/4

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N2 - This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mm ×3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power.

AB - This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mm ×3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power.

KW - Digital signal processor

KW - Dual-core processor

KW - Register organization

KW - Variable-length instruction encoding

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ER -

A unified processor architecture for RISC & VLIW DSP

Abstract

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Keywords

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