@inproceedings{df050523df1249a699afceb331b8ca76,
title = "A two-level pipelined systolic array chip for computing the discrete cosine transform",
abstract = "A two-level pipelined systolic array chip for the discrete cosine transform (DCT) is presented. This chip is based on a new memory-based systolic algorithm which not only uses small ROM's and adders to realize the multiplications but also owns good data locality. Therefore, this chip possesses outstanding performance in hardware cost, computing speeds, the number of I/O channels, and the I/O bandwidth.",
author = "Jiun-In Guo and Liu, {Chi Min} and Jen, {Chein Wei}",
year = "1993",
month = jan,
day = "1",
doi = "10.1109/VTSA.1993.263606",
language = "English",
series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "199--203",
booktitle = "1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers",
address = "United States",
note = "1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 ; Conference date: 12-05-1993 Through 14-05-1993",
}