A Two-Directional BigData Sorting Architecture on FPGA

Bo Cheng C. Lai; Chun Yen Chen; Yi Da Hsin; Bo Yen Lin

doi:10.1109/LCA.2020.2993040

A Two-Directional BigData Sorting Architecture on FPGA

Bo Cheng C. Lai, Chun Yen Chen, Yi Da Hsin, Bo Yen Lin

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

Sorting is pivotal data analytics and becomes challenging with intensive computation on drastically growing data volume. Sorting on FPGA has shown superior throughput, but the limited in-system memory causes vast data transferring to/from external storage when handling a large dataset. We propose a two-directional sorting (2DSort) architecture which sorts data sequences on both horizontal and vertical directions. 2DSort significantly reduces the costly data transmission by tracking the data on FPGA and writes back the data to external storage when the final sorting position is determined. 2DSort shows average 38.5% runtime enhancement in comparison to state-of-the-art bigdata sorting engine on FPGA.

Original language	English
Journal	IEEE Computer Architecture Letters
DOIs	https://doi.org/10.1109/LCA.2020.2993040
State	Accepted/In press - 1 Jan 2020

Keywords

B.2 Arithmetic and Logic Structures
B.5.1.c Data-path design
B.6.1.c Logic arrays
C.0.e System architectures
C.3.e Reconfigurable hardware
integration and modeling

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AU - Chen, Chun Yen

AU - Hsin, Yi Da

AU - Lin, Bo Yen

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AB - Sorting is pivotal data analytics and becomes challenging with intensive computation on drastically growing data volume. Sorting on FPGA has shown superior throughput, but the limited in-system memory causes vast data transferring to/from external storage when handling a large dataset. We propose a two-directional sorting (2DSort) architecture which sorts data sequences on both horizontal and vertical directions. 2DSort significantly reduces the costly data transmission by tracking the data on FPGA and writes back the data to external storage when the final sorting position is determined. 2DSort shows average 38.5% runtime enhancement in comparison to state-of-the-art bigdata sorting engine on FPGA.

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KW - B.5.1.c Data-path design

KW - B.6.1.c Logic arrays

KW - C.0.e System architectures

KW - C.3.e Reconfigurable hardware

KW - integration and modeling

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SN - 1556-6056

JO - IEEE Computer Architecture Letters

JF - IEEE Computer Architecture Letters

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A Two-Directional BigData Sorting Architecture on FPGA

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Keywords

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