A true random-based differential power analysis countermeasure circuit for an AES engine

Po Chun Liu*, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    27 Scopus citations

    Abstract

    The differential power analysis (DPA) has become a big threat to crypto chips since it can efficiently disclose the secret key without much effort. Several methods have been proposed in literatures to resist the DPA attack, but they largely increase the hardware cost and severely degrade the throughput. In this brief, a security problem based on ring oscillators is resolved by a new architecture with self-generated true random sequence. The true random-based architecture is implemented with an Advanced Encryption Standard (AES) crypto engine using UMC 90-nm CMOS technology. The DPA-resistant AES engine can achieve 2.97-Gb/s throughput at an operating frequency of 255 MHz with a 0.104-mm 2 cell area. The proposed DPA countermeasure circuit has only 6.2% area and 18.5% power overhead without throughput degradation.

    Original languageEnglish
    Article number6135779
    Pages (from-to)103-107
    Number of pages5
    JournalIEEE Transactions on Circuits and Systems I: Regular Papers
    Volume59
    Issue number2
    DOIs
    StatePublished - Feb 2012

    Keywords

    • Advanced Encryption Standard (AES)
    • cryptography
    • differential power analysis (DPA)
    • ring oscillators
    • true random number generator

    Fingerprint

    Dive into the research topics of 'A true random-based differential power analysis countermeasure circuit for an AES engine'. Together they form a unique fingerprint.

    Cite this