A trainable analog neural chip for image compression

Chia Fen Chang; Bing J. Sheu; Wai-Chi  Fang; Joongho Choi

doi:10.1109/CICC.1991.164010

A trainable analog neural chip for image compression

Chia Fen Chang^*, Bing J. Sheu, Wai-Chi Fang, Joongho Choi

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Video motion estimation and high-ratio image compression are two key data processing steps for advanced television systems and imaging machines. The detailed circuit design of a vector quantization chip with the full-search scheme is presented. Each 5 × 5 image block with 256-pixel gray levels can be quantized into the 6-b codebook by a prototye chip of 4.6 mm × 6.8 mm in a 2-μm scalable MOSIS technology. A speedup factor of 750 over a Sun-3/60 workstation has been obtained. Adaptive codebook learning can be performed with a digital coprocessor.

Original language	English
Title of host publication	Proceedings of the Custom Integrated Circuits Conference
Publisher	Publ by IEEE
ISBN (Print)	0780300157
DOIs	https://doi.org/10.1109/CICC.1991.164010
State	Published - 1 Dec 1991
Event	Proceedings of the IEEE 1991 Custom Integrated Circuits Conference - San Diego, CA, USA Duration: 12 May 1991 → 15 May 1991

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Conference

Conference	Proceedings of the IEEE 1991 Custom Integrated Circuits Conference
City	San Diego, CA, USA
Period	12/05/91 → 15/05/91

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10.1109/CICC.1991.164010

Cite this

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title = "A trainable analog neural chip for image compression",

abstract = "Video motion estimation and high-ratio image compression are two key data processing steps for advanced television systems and imaging machines. The detailed circuit design of a vector quantization chip with the full-search scheme is presented. Each 5 × 5 image block with 256-pixel gray levels can be quantized into the 6-b codebook by a prototye chip of 4.6 mm × 6.8 mm in a 2-μm scalable MOSIS technology. A speedup factor of 750 over a Sun-3/60 workstation has been obtained. Adaptive codebook learning can be performed with a digital coprocessor.",

author = "Chang, {Chia Fen} and Sheu, {Bing J.} and Wai-Chi Fang and Joongho Choi",

year = "1991",

month = dec,

day = "1",

doi = "10.1109/CICC.1991.164010",

language = "English",

isbn = "0780300157",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Publ by IEEE",

booktitle = "Proceedings of the Custom Integrated Circuits Conference",

note = "Proceedings of the IEEE 1991 Custom Integrated Circuits Conference ; Conference date: 12-05-1991 Through 15-05-1991",

}

Chang, CF, Sheu, BJ, Fang, W-C & Choi, J 1991, A trainable analog neural chip for image compression. in Proceedings of the Custom Integrated Circuits Conference. Proceedings of the Custom Integrated Circuits Conference, Publ by IEEE, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, San Diego, CA, USA, 12/05/91. https://doi.org/10.1109/CICC.1991.164010

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AU - Sheu, Bing J.

AU - Fang, Wai-Chi

AU - Choi, Joongho

PY - 1991/12/1

Y1 - 1991/12/1

N2 - Video motion estimation and high-ratio image compression are two key data processing steps for advanced television systems and imaging machines. The detailed circuit design of a vector quantization chip with the full-search scheme is presented. Each 5 × 5 image block with 256-pixel gray levels can be quantized into the 6-b codebook by a prototye chip of 4.6 mm × 6.8 mm in a 2-μm scalable MOSIS technology. A speedup factor of 750 over a Sun-3/60 workstation has been obtained. Adaptive codebook learning can be performed with a digital coprocessor.

AB - Video motion estimation and high-ratio image compression are two key data processing steps for advanced television systems and imaging machines. The detailed circuit design of a vector quantization chip with the full-search scheme is presented. Each 5 × 5 image block with 256-pixel gray levels can be quantized into the 6-b codebook by a prototye chip of 4.6 mm × 6.8 mm in a 2-μm scalable MOSIS technology. A speedup factor of 750 over a Sun-3/60 workstation has been obtained. Adaptive codebook learning can be performed with a digital coprocessor.

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U2 - 10.1109/CICC.1991.164010

DO - 10.1109/CICC.1991.164010

M3 - Conference contribution

AN - SCOPUS:0026391925

SN - 0780300157

T3 - Proceedings of the Custom Integrated Circuits Conference

BT - Proceedings of the Custom Integrated Circuits Conference

PB - Publ by IEEE

T2 - Proceedings of the IEEE 1991 Custom Integrated Circuits Conference

Y2 - 12 May 1991 through 15 May 1991

ER -

A trainable analog neural chip for image compression

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