Abstract
A threshold-embedded offset calibration technique for inverter-based analog-to-digital converter (ADC) is presented. This work presents a background calibration technique for trimming the input-referred offsets of the comparators without interrupting the ADC's normal operation. Moreover, a folding flash architecture is employed to save the conversion power. The proposed calibration approach is based on the time-domain comparison. The random input-referred offsets of the comparators are converted to phase difference and detected by time-domain comparators. Simulation results show that the proposed compensation technique is validated. After calibration, the effective number of bits (ENOB) can be significantly improved from 3.4 bit to 5.7 bit.
Original language | English |
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Pages | 25-28 |
Number of pages | 4 |
DOIs | |
State | Published - 2013 |
Event | 2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013 - Kaohsiung, Taiwan Duration: 25 Feb 2013 → 26 Feb 2013 |
Conference
Conference | 2013 IEEE International Symposium on Next-Generation Electronics, ISNE 2013 |
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Country/Territory | Taiwan |
City | Kaohsiung |
Period | 25/02/13 → 26/02/13 |