A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse

Taylor Barton; Shea Smith; Yu Hao; Ryan Watson; Kyle Rogers; Parker Allred; Bibhu Datta Sahoo; Nancy Fulda; Jordan T. Yorgason; Karl F. Warnick; Mau Chung Frank Chang; Yen Cheng Kuan; Shiuh Hua Wood Chiang

doi:10.1109/LSSC.2024.3384762

A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse

Taylor Barton
, Shea Smith
, Yu Hao
, Ryan Watson
, Kyle Rogers
, Parker Allred
, Bibhu Datta Sahoo
, Nancy Fulda
, Jordan T. Yorgason
, Karl F. Warnick
, Mau Chung Frank Chang
, Yen Cheng Kuan^*
, Shiuh Hua Wood Chiang^*

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

The design and measurement of a time-domain analog spiking neuron is described. The proposed neuron leverages time-domain processing using voltage-controlled oscillators (VCOs) and a time-domain comparator to integrate the input spike and trigger the output spike. A novel leaky circuit uses a phase-locked loop (PLL) to drive the phase difference between the two VCOs toward zero. A weighted capacitive digital-to-analog converter (CDAC) synapse merges the input spikes and phase-frequency detector (PFD) outputs to generate the VCO control voltage. The neuron is implemented in a 28-nm CMOS technology and operates under a subthreshold supply voltage of 0.35 V. Occupying 154~mu {mathrm{ m}}{2} , measurement shows a maximum spike rate of 5.5 MHz and energy consumption of 159 fJ/spike.

Original language	English
Pages (from-to)	143-146
Number of pages	4
Journal	IEEE Solid-State Circuits Letters
Volume	7
DOIs	https://doi.org/10.1109/LSSC.2024.3384762
State	Published - 2024

Keywords

Analog neuron
capacitive digital-to-analog converter (CDAC)
phase-locked loop (PLL)
spiking neuron
time-domain circuit
voltage-controlled oscillator (VCO)

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/LSSC.2024.3384762

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Barton, T., Smith, S., Hao, Y., Watson, R., Rogers, K., Allred, P., Sahoo, B. D., Fulda, N., Yorgason, J. T., Warnick, K. F., Chang, M. C. F., Kuan, Y. C., & Chiang, S. H. W. (2024). A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse. IEEE Solid-State Circuits Letters, 7, 143-146. https://doi.org/10.1109/LSSC.2024.3384762

@article{e4335916f5d441ebb6287567abdc646d,

title = "A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse",

abstract = "The design and measurement of a time-domain analog spiking neuron is described. The proposed neuron leverages time-domain processing using voltage-controlled oscillators (VCOs) and a time-domain comparator to integrate the input spike and trigger the output spike. A novel leaky circuit uses a phase-locked loop (PLL) to drive the phase difference between the two VCOs toward zero. A weighted capacitive digital-to-analog converter (CDAC) synapse merges the input spikes and phase-frequency detector (PFD) outputs to generate the VCO control voltage. The neuron is implemented in a 28-nm CMOS technology and operates under a subthreshold supply voltage of 0.35 V. Occupying 154\textasciitilde{}mu \{mathrm\{ m\}\}\{2\} , measurement shows a maximum spike rate of 5.5 MHz and energy consumption of 159 fJ/spike.",

keywords = "Analog neuron, capacitive digital-to-analog converter (CDAC), phase-locked loop (PLL), spiking neuron, time-domain circuit, voltage-controlled oscillator (VCO)",

author = "Taylor Barton and Shea Smith and Yu Hao and Ryan Watson and Kyle Rogers and Parker Allred and Sahoo, \{Bibhu Datta\} and Nancy Fulda and Yorgason, \{Jordan T.\} and Warnick, \{Karl F.\} and Chang, \{Mau Chung Frank\} and Kuan, \{Yen Cheng\} and Chiang, \{Shiuh Hua Wood\}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.",

year = "2024",

doi = "10.1109/LSSC.2024.3384762",

language = "English",

volume = "7",

pages = "143--146",

journal = "IEEE Solid-State Circuits Letters",

issn = "2573-9603",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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AU - Hao, Yu

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AU - Rogers, Kyle

AU - Allred, Parker

AU - Sahoo, Bibhu Datta

AU - Fulda, Nancy

AU - Yorgason, Jordan T.

AU - Warnick, Karl F.

AU - Chang, Mau Chung Frank

AU - Kuan, Yen Cheng

AU - Chiang, Shiuh Hua Wood

PY - 2024

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AB - The design and measurement of a time-domain analog spiking neuron is described. The proposed neuron leverages time-domain processing using voltage-controlled oscillators (VCOs) and a time-domain comparator to integrate the input spike and trigger the output spike. A novel leaky circuit uses a phase-locked loop (PLL) to drive the phase difference between the two VCOs toward zero. A weighted capacitive digital-to-analog converter (CDAC) synapse merges the input spikes and phase-frequency detector (PFD) outputs to generate the VCO control voltage. The neuron is implemented in a 28-nm CMOS technology and operates under a subthreshold supply voltage of 0.35 V. Occupying 154~mu {mathrm{ m}}{2} , measurement shows a maximum spike rate of 5.5 MHz and energy consumption of 159 fJ/spike.

KW - Analog neuron

KW - capacitive digital-to-analog converter (CDAC)

KW - phase-locked loop (PLL)

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KW - time-domain circuit

KW - voltage-controlled oscillator (VCO)

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M3 - Article

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SN - 2573-9603

VL - 7

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JO - IEEE Solid-State Circuits Letters

JF - IEEE Solid-State Circuits Letters

ER -

A Subthreshold Time-Domain Analog Spiking Neuron With PLL-Based Leak Circuit and Capacitive DAC Synapse

Abstract

Keywords

UN SDGs

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