A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper

Yi Wei Chiu; Yu Hao Hu; Jun Kai Zhao; Shyh-Jye Jou; Ching Te Chuang

doi:10.1109/ISCAS.2016.7527415

A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper

Yi Wei Chiu, Yu Hao Hu, Jun Kai Zhao, Shyh-Jye Jou, Ching Te Chuang

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (VMIN). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read VMIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve VMIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read VMIN by 9% to 21% at low supply voltages.

Original language	English
Title of host publication	ISCAS 2016 - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1014-1017
Number of pages	4
ISBN (Electronic)	9781479953400
DOIs	https://doi.org/10.1109/ISCAS.2016.7527415
State	Published - 29 Jul 2016
Event	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: 22 May 2016 → 25 May 2016

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2016-July
ISSN (Print)	0271-4310

Conference

Conference	2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Country/Territory	Canada
City	Montreal
Period	22/05/16 → 25/05/16

Access to Document

10.1109/ISCAS.2016.7527415

Cite this

Chiu, Y. W., Hu, Y. H., Zhao, J. K., Jou, S.-J., & Chuang, C. T. (2016). A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems (pp. 1014-1017). Article 7527415 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2016.7527415

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title = "A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper",

abstract = "We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (VMIN). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read VMIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve VMIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read VMIN by 9% to 21% at low supply voltages.",

author = "Chiu, {Yi Wei} and Hu, {Yu Hao} and Zhao, {Jun Kai} and Shyh-Jye Jou and Chuang, {Ching Te}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 ; Conference date: 22-05-2016 Through 25-05-2016",

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doi = "10.1109/ISCAS.2016.7527415",

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Chiu, YW, Hu, YH, Zhao, JK, Jou, S-J & Chuang, CT 2016, A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. in ISCAS 2016 - IEEE International Symposium on Circuits and Systems., 7527415, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2016-July, Institute of Electrical and Electronics Engineers Inc., pp. 1014-1017, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montreal, Canada, 22/05/16. https://doi.org/10.1109/ISCAS.2016.7527415

A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. / Chiu, Yi Wei; Hu, Yu Hao; Zhao, Jun Kai et al.
ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2016. p. 1014-1017 7527415 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2016-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper

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AU - Zhao, Jun Kai

AU - Jou, Shyh-Jye

AU - Chuang, Ching Te

PY - 2016/7/29

Y1 - 2016/7/29

N2 - We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (VMIN). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read VMIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve VMIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read VMIN by 9% to 21% at low supply voltages.

AB - We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (VMIN). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read VMIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve VMIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read VMIN by 9% to 21% at low supply voltages.

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Chiu YW, Hu YH, Zhao JK, Jou SJ, Chuang CT. A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. In ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2016. p. 1014-1017. 7527415. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2016.7527415

A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper

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