A Stack-Based In-Pixel Storage Circuit for SPAD Photon Counting

Tzu Yun Huang, Hsi Hao Huang, Chun Hsien Liu, Sheng Di Lin, Chen Yi Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Single-photon avalanche diodes (SPADs) have attracted a lot of attention these days because of the ability to detect a single photon for many emerging applications. However, planar SPAD sensor arrays often suffer from serious photon loss because the readout bottleneck dominates the overall dead time. This paper presents a stack-based in-pixel storage circuit for high-throughput SPAD imaging. The proposed circuit helps a SPAD imaging chip solve the buffer saturation problem and reduces its dead time by half compared to single-bit storage. Fabricated in TSMC HV 0.18μm CMOS technology, each pixel in the SPAD array can record at most three photons in 50 ns, resulting in 40Mfps. The minimum integration time to form an 8-bit image is reduced to 6.4μs while maintaining global shutter exposure.

Original languageEnglish
Title of host publicationISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665451093
DOIs
StatePublished - 2023
Event56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 - Monterey, United States
Duration: 21 May 202325 May 2023

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2023-May
ISSN (Print)0271-4310

Conference

Conference56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Country/TerritoryUnited States
CityMonterey
Period21/05/2325/05/23

Keywords

  • SPAD
  • SPC
  • high-speed camera
  • in-pixel storage

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