@inproceedings{f97515e6a0a841eaa65e200e931166aa,
title = "A spread spectrum clock generator with phase-rotation algorithm for 6Gbps clock and data recovery",
abstract = "A low jitter phase-lock-loop (PLL) and a proposed spread-spectrum clock method for Serial ATA with phase rotation is presented The low jitter PLL uses error amplifier to resolve the current mismatch in charge pump and the 3 rd order loop filter is adopted to reduce the reference spur. A passive resistance is presented in our design to reduce the Kvco. Our spread spectrum clock generator (SSCG) for Serial ATA specification is down spread 5000 ppm with a triangular waveform and the modulation frequency is 30-33KHz. Spread-spectrum technique using PLL with a Δ Σ modulator and phase rotation algorithm is reported. The proposed circuit has been designed in a 90-nm CMOS process. The non-spread spectrum clocking has a peak to peak jitter of 512fs and consumes 5.87mW at 1.4GHz. The EMI reduction is about 19.24dB.",
keywords = "EMI, PLL, Serial ATA, SSCG",
author = "Lin, {Chi Hsien} and Huang, {Yen Ying} and Li, {Shu Rung} and Cheng, {Yuan Pu} and Shyh-Jye Jou",
year = "2009",
month = dec,
day = "1",
doi = "10.1109/ASICON.2009.5351414",
language = "English",
isbn = "9781424438686",
series = "ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC",
pages = "387--390",
booktitle = "ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC",
note = "2009 8th IEEE International Conference on ASIC, ASICON 2009 ; Conference date: 20-10-2009 Through 23-10-2009",
}