A spread spectrum clock generator with phase-rotation algorithm for 6Gbps clock and data recovery

Chi Hsien Lin*, Yen Ying Huang, Shu Rung Li, Yuan Pu Cheng, Shyh-Jye Jou

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    A low jitter phase-lock-loop (PLL) and a proposed spread-spectrum clock method for Serial ATA with phase rotation is presented The low jitter PLL uses error amplifier to resolve the current mismatch in charge pump and the 3 rd order loop filter is adopted to reduce the reference spur. A passive resistance is presented in our design to reduce the Kvco. Our spread spectrum clock generator (SSCG) for Serial ATA specification is down spread 5000 ppm with a triangular waveform and the modulation frequency is 30-33KHz. Spread-spectrum technique using PLL with a Δ Σ modulator and phase rotation algorithm is reported. The proposed circuit has been designed in a 90-nm CMOS process. The non-spread spectrum clocking has a peak to peak jitter of 512fs and consumes 5.87mW at 1.4GHz. The EMI reduction is about 19.24dB.

    Original languageEnglish
    Title of host publicationASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
    Pages387-390
    Number of pages4
    DOIs
    StatePublished - 1 Dec 2009
    Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China
    Duration: 20 Oct 200923 Oct 2009

    Publication series

    NameASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

    Conference

    Conference2009 8th IEEE International Conference on ASIC, ASICON 2009
    Country/TerritoryChina
    CityChangsha
    Period20/10/0923/10/09

    Keywords

    • EMI
    • PLL
    • Serial ATA
    • SSCG

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