A single-ended disturb-free 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing

Ming Hsien Tu*, Jihi Yu Lin, Ming Chien Tsai, Chien Yu Lu, Yuh Jiun Lin, Meng Hsueh Wang, Huan Shun Huang, Kuen Di Lee, Wei Chiang Shih, Shyh-Jye Jou, Ching Te Chuang

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    138 Scopus citations

    Abstract

    This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V DD down to 0.35 V (∼ 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 μW power. Data is held down to 0.275 V with 2.29 μW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V DD around/above 1.0 V.

    Original languageEnglish
    Article number6183492
    Pages (from-to)1469-1482
    Number of pages14
    JournalIEEE Journal of Solid-State Circuits
    Volume47
    Issue number6
    DOIs
    StatePublished - 18 Apr 2012

    Keywords

    • Low power
    • low voltage
    • negative bit-line (BL)
    • subthreshold SRAM cell
    • timing tracing

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