A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique

Tzu I. Tsai; Tien-Sheng Chao; Horng-Chih Lin; Tiao Yuan Huang; Yun Jie Wei

doi:10.1109/INEC.2011.5991710

A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique

Tzu I. Tsai^*, Tien-Sheng Chao, Horng-Chih Lin, Tiao Yuan Huang, Yun Jie Wei

^*Corresponding author for this work

Department of Electrophysics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

We present a simple modified double-patterning (DP) technique with I-line stepper to define 23 nm nano-scale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with gate length down to 69 nm. With this approach, polycrystalline silicon (poly-Si) gate with line width down to 70 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography.

Original language	English
Title of host publication	4th IEEE International NanoElectronics Conference, INEC 2011
DOIs	https://doi.org/10.1109/INEC.2011.5991710
State	Published - 26 Sep 2011
Event	4th IEEE International Nanoelectronics Conference, INEC 2011 - Tao-Yuan, Taiwan Duration: 21 Jun 2011 → 24 Jun 2011

Publication series

Name	Proceedings - International NanoElectronics Conference, INEC
ISSN (Print)	2159-3523

Conference

Conference	4th IEEE International Nanoelectronics Conference, INEC 2011
Country/Territory	Taiwan
City	Tao-Yuan
Period	21/06/11 → 24/06/11

Keywords

double pattern
MOSFETs
photoresist ashing

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10.1109/INEC.2011.5991710

Cite this

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title = "A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique",

abstract = "We present a simple modified double-patterning (DP) technique with I-line stepper to define 23 nm nano-scale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with gate length down to 69 nm. With this approach, polycrystalline silicon (poly-Si) gate with line width down to 70 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography.",

keywords = "double pattern, MOSFETs, photoresist ashing",

author = "Tsai, {Tzu I.} and Tien-Sheng Chao and Horng-Chih Lin and Huang, {Tiao Yuan} and Wei, {Yun Jie}",

year = "2011",

month = sep,

day = "26",

doi = "10.1109/INEC.2011.5991710",

language = "English",

isbn = "9781457703799",

series = "Proceedings - International NanoElectronics Conference, INEC",

booktitle = "4th IEEE International NanoElectronics Conference, INEC 2011",

note = "4th IEEE International Nanoelectronics Conference, INEC 2011 ; Conference date: 21-06-2011 Through 24-06-2011",

}

Tsai, TI, Chao, T-S , Lin, H-C, Huang, TY & Wei, YJ 2011, A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique. in 4th IEEE International NanoElectronics Conference, INEC 2011., 5991710, Proceedings - International NanoElectronics Conference, INEC, 4th IEEE International Nanoelectronics Conference, INEC 2011, Tao-Yuan, Taiwan, 21/06/11. https://doi.org/10.1109/INEC.2011.5991710

A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique. / Tsai, Tzu I.; Chao, Tien-Sheng ; Lin, Horng-Chih et al.
4th IEEE International NanoElectronics Conference, INEC 2011. 2011. 5991710 (Proceedings - International NanoElectronics Conference, INEC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique

AU - Tsai, Tzu I.

AU - Chao, Tien-Sheng

AU - Lin, Horng-Chih

AU - Huang, Tiao Yuan

AU - Wei, Yun Jie

PY - 2011/9/26

Y1 - 2011/9/26

N2 - We present a simple modified double-patterning (DP) technique with I-line stepper to define 23 nm nano-scale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with gate length down to 69 nm. With this approach, polycrystalline silicon (poly-Si) gate with line width down to 70 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography.

AB - We present a simple modified double-patterning (DP) technique with I-line stepper to define 23 nm nano-scale structures and have successfully fabricated n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with gate length down to 69 nm. With this approach, polycrystalline silicon (poly-Si) gate with line width down to 70 nm could be formed with good control, which far exceeds the resolution limit of conventional I-line lithography.

KW - double pattern

KW - MOSFETs

KW - photoresist ashing

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U2 - 10.1109/INEC.2011.5991710

DO - 10.1109/INEC.2011.5991710

M3 - Conference contribution

AN - SCOPUS:80053001585

SN - 9781457703799

T3 - Proceedings - International NanoElectronics Conference, INEC

BT - 4th IEEE International NanoElectronics Conference, INEC 2011

T2 - 4th IEEE International Nanoelectronics Conference, INEC 2011

Y2 - 21 June 2011 through 24 June 2011

ER -

A simple method for forming sub-30 nm gate patterns with modified I-line double patterning technique

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Publication series

Conference

Keywords

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