A series stacked FinFET structure for digital low dropout regulators with minimum energy point technique for 37.5% energy reduction in Cortex M0 processor

Nan Hsiung Tseng; Bo Kuan Wu; Tzu Ping Huang; Cheng Yen Lee; Ke Horng Chen; Ying Hsi Lin; Shian Ru Lin; Tsung Yen Tsai

doi:10.1109/ISCAS51556.2021.9401222

A series stacked FinFET structure for digital low dropout regulators with minimum energy point technique for 37.5% energy reduction in Cortex M0 processor

Nan Hsiung Tseng, Bo Kuan Wu, Tzu Ping Huang, Cheng Yen Lee, Ke Horng Chen, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

The series stacked (SS) FinFET structure is used in digital low dropout (DLDO) regulators to withstand high input voltages and implement dynamic voltage scaling (DVS) technique with minimum energy point (MEP) technique. Through an additional delay consideration in MEP, both energy reduction and performance of the Cortex M0 processor can achieve 34.5pJ/cycle at 0.5V. Maximum energy reduction is about 37.5% and the supplying voltage varies from 0.4V to 0.775V with a search time of 2.5μs for each voltage step. The proposed SS-DLDO has fast settling time and low output voltage ripple of 1.5μs and 5mV, respectively.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728192017
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401222
State	Published - May 2021
Event	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2021-May
ISSN (Print)	0271-4310

Conference

Conference	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/Territory	Korea, Republic of
City	Daegu
Period	22/05/21 → 28/05/21

Keywords

Dynamic voltage scaling (DVS) technique
Minimum energy point (MEP) technique
Series stacked (SS) FinFET

Access to Document

10.1109/ISCAS51556.2021.9401222

Cite this

Tseng, N. H., Wu, B. K., Huang, T. P., Lee, C. Y., Chen, K. H., Lin, Y. H., Lin, S. R., & Tsai, T. Y. (2021). A series stacked FinFET structure for digital low dropout regulators with minimum energy point technique for 37.5% energy reduction in Cortex M0 processor. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings Article 9401222 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS51556.2021.9401222

Tseng, Nan Hsiung ; Wu, Bo Kuan ; Huang, Tzu Ping et al. / A series stacked FinFET structure for digital low dropout regulators with minimum energy point technique for 37.5% energy reduction in Cortex M0 processor. 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{e6f4cc1a05b446e3becff9782892fb3c,

title = "A series stacked FinFET structure for digital low dropout regulators with minimum energy point technique for 37.5% energy reduction in Cortex M0 processor",

abstract = "The series stacked (SS) FinFET structure is used in digital low dropout (DLDO) regulators to withstand high input voltages and implement dynamic voltage scaling (DVS) technique with minimum energy point (MEP) technique. Through an additional delay consideration in MEP, both energy reduction and performance of the Cortex M0 processor can achieve 34.5pJ/cycle at 0.5V. Maximum energy reduction is about 37.5% and the supplying voltage varies from 0.4V to 0.775V with a search time of 2.5μs for each voltage step. The proposed SS-DLDO has fast settling time and low output voltage ripple of 1.5μs and 5mV, respectively.",

keywords = "Dynamic voltage scaling (DVS) technique, Minimum energy point (MEP) technique, Series stacked (SS) FinFET",

author = "Tseng, {Nan Hsiung} and Wu, {Bo Kuan} and Huang, {Tzu Ping} and Lee, {Cheng Yen} and Chen, {Ke Horng} and Lin, {Ying Hsi} and Lin, {Shian Ru} and Tsai, {Tsung Yen}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",

year = "2021",

month = may,

doi = "10.1109/ISCAS51556.2021.9401222",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings",

address = "美國",

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Tseng, NH, Wu, BK, Huang, TP, Lee, CY, Chen, KH, Lin, YH, Lin, SR & Tsai, TY 2021, A series stacked FinFET structure for digital low dropout regulators with minimum energy point technique for 37.5% energy reduction in Cortex M0 processor. in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401222, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, Institute of Electrical and Electronics Engineers Inc., 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401222

A series stacked FinFET structure for digital low dropout regulators with minimum energy point technique for 37.5% energy reduction in Cortex M0 processor. / Tseng, Nan Hsiung; Wu, Bo Kuan; Huang, Tzu Ping et al.
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9401222 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A series stacked FinFET structure for digital low dropout regulators with minimum energy point technique for 37.5% energy reduction in Cortex M0 processor

AU - Tseng, Nan Hsiung

AU - Wu, Bo Kuan

AU - Huang, Tzu Ping

AU - Lee, Cheng Yen

AU - Chen, Ke Horng

AU - Lin, Ying Hsi

AU - Lin, Shian Ru

AU - Tsai, Tsung Yen

PY - 2021/5

Y1 - 2021/5

N2 - The series stacked (SS) FinFET structure is used in digital low dropout (DLDO) regulators to withstand high input voltages and implement dynamic voltage scaling (DVS) technique with minimum energy point (MEP) technique. Through an additional delay consideration in MEP, both energy reduction and performance of the Cortex M0 processor can achieve 34.5pJ/cycle at 0.5V. Maximum energy reduction is about 37.5% and the supplying voltage varies from 0.4V to 0.775V with a search time of 2.5μs for each voltage step. The proposed SS-DLDO has fast settling time and low output voltage ripple of 1.5μs and 5mV, respectively.

AB - The series stacked (SS) FinFET structure is used in digital low dropout (DLDO) regulators to withstand high input voltages and implement dynamic voltage scaling (DVS) technique with minimum energy point (MEP) technique. Through an additional delay consideration in MEP, both energy reduction and performance of the Cortex M0 processor can achieve 34.5pJ/cycle at 0.5V. Maximum energy reduction is about 37.5% and the supplying voltage varies from 0.4V to 0.775V with a search time of 2.5μs for each voltage step. The proposed SS-DLDO has fast settling time and low output voltage ripple of 1.5μs and 5mV, respectively.

KW - Dynamic voltage scaling (DVS) technique

KW - Minimum energy point (MEP) technique

KW - Series stacked (SS) FinFET

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021

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ER -

Tseng NH, Wu BK, Huang TP, Lee CY, Chen KH, Lin YH et al. A series stacked FinFET structure for digital low dropout regulators with minimum energy point technique for 37.5% energy reduction in Cortex M0 processor. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9401222. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS51556.2021.9401222

A series stacked FinFET structure for digital low dropout regulators with minimum energy point technique for 37.5% energy reduction in Cortex M0 processor

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