A resolution-reconfigurable and power scalable SAR ADC with partially thermometer coded DAC

Hao Min Lin; Chih Hsuan Lin; Kuei-Ann Wen

doi:10.25046/aj030609

A resolution-reconfigurable and power scalable SAR ADC with partially thermometer coded DAC

Hao Min Lin^*, Chih Hsuan Lin, Kuei-Ann Wen

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

Power consumption is becoming more and more important in the Internet of Things (IOT). The ADC is the main power hungry in multi-sensor electronic systems and effectively reducing ADC power consumption without affecting ADC characteristics is an important. This paper is extended from the conference paper. The segmented SAR ADC presents reconfigurable 9 to 12-bit DACs with rail-to rail input range, and 3 MSB segmented capacitor arrays are used to improve linearity and lower switching energy than conventional architectures. The dual supply voltage skill separating digital and analog voltage is implemented for achieving low power consumption. In the provided 9 to 12 bits mode, this structure consumes 2.5, 2.8, 3.9 and 9.7 uW and SNDR achieve 52.3, 57.7, 63.2 and 68.6 db respectively, resulting in figure of merit (FoM) 148, 88.8, 66.3 and 88.4 fJ/conversion-step.

Original language	English
Pages (from-to)	89-96
Number of pages	8
Journal	Advances in Science, Technology and Engineering Systems
Volume	3
Issue number	6
DOIs	https://doi.org/10.25046/aj030609
State	Published - 1 Jan 2018

Keywords

Reconfigurable
SAR ADC
Thermometer Coded

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10.25046/aj030609

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title = "A resolution-reconfigurable and power scalable SAR ADC with partially thermometer coded DAC",

abstract = "Power consumption is becoming more and more important in the Internet of Things (IOT). The ADC is the main power hungry in multi-sensor electronic systems and effectively reducing ADC power consumption without affecting ADC characteristics is an important. This paper is extended from the conference paper. The segmented SAR ADC presents reconfigurable 9 to 12-bit DACs with rail-to rail input range, and 3 MSB segmented capacitor arrays are used to improve linearity and lower switching energy than conventional architectures. The dual supply voltage skill separating digital and analog voltage is implemented for achieving low power consumption. In the provided 9 to 12 bits mode, this structure consumes 2.5, 2.8, 3.9 and 9.7 uW and SNDR achieve 52.3, 57.7, 63.2 and 68.6 db respectively, resulting in figure of merit (FoM) 148, 88.8, 66.3 and 88.4 fJ/conversion-step.",

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AU - Lin, Hao Min

AU - Lin, Chih Hsuan

AU - Wen, Kuei-Ann

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N2 - Power consumption is becoming more and more important in the Internet of Things (IOT). The ADC is the main power hungry in multi-sensor electronic systems and effectively reducing ADC power consumption without affecting ADC characteristics is an important. This paper is extended from the conference paper. The segmented SAR ADC presents reconfigurable 9 to 12-bit DACs with rail-to rail input range, and 3 MSB segmented capacitor arrays are used to improve linearity and lower switching energy than conventional architectures. The dual supply voltage skill separating digital and analog voltage is implemented for achieving low power consumption. In the provided 9 to 12 bits mode, this structure consumes 2.5, 2.8, 3.9 and 9.7 uW and SNDR achieve 52.3, 57.7, 63.2 and 68.6 db respectively, resulting in figure of merit (FoM) 148, 88.8, 66.3 and 88.4 fJ/conversion-step.

AB - Power consumption is becoming more and more important in the Internet of Things (IOT). The ADC is the main power hungry in multi-sensor electronic systems and effectively reducing ADC power consumption without affecting ADC characteristics is an important. This paper is extended from the conference paper. The segmented SAR ADC presents reconfigurable 9 to 12-bit DACs with rail-to rail input range, and 3 MSB segmented capacitor arrays are used to improve linearity and lower switching energy than conventional architectures. The dual supply voltage skill separating digital and analog voltage is implemented for achieving low power consumption. In the provided 9 to 12 bits mode, this structure consumes 2.5, 2.8, 3.9 and 9.7 uW and SNDR achieve 52.3, 57.7, 63.2 and 68.6 db respectively, resulting in figure of merit (FoM) 148, 88.8, 66.3 and 88.4 fJ/conversion-step.

KW - Reconfigurable

KW - SAR ADC

KW - Thermometer Coded

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A resolution-reconfigurable and power scalable SAR ADC with partially thermometer coded DAC

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Keywords

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