A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform

Bing-Fei Wu; Chung Fu Lin

doi:10.1109/ISCAS.2003.1206078

A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform

Bing-Fei Wu^*, Chung Fu Lin

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

22 Scopus citations

Abstract

In this paper, we propose a fast pipeline VLSI architecture for 1-D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511x2.510 mm², and 150 MHz, respectively.

Original language	English
Article number	1206078
Pages (from-to)	732-735
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
DOIs	https://doi.org/10.1109/ISCAS.2003.1206078
State	Published - 25 May 2003
Event	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003

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title = "A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform",

abstract = "In this paper, we propose a fast pipeline VLSI architecture for 1-D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511x2.510 mm2, and 150 MHz, respectively.",

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AU - Lin, Chung Fu

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N2 - In this paper, we propose a fast pipeline VLSI architecture for 1-D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511x2.510 mm2, and 150 MHz, respectively.

AB - In this paper, we propose a fast pipeline VLSI architecture for 1-D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predictor and updater into one single step. Based on this modified algorithm, we explore the data dependency of the input and output signals, and thus make the pipeline design more efficiently for hardware implementation under the same processor elements proposed in previous works. Moreover, the inverse DWT case also adopts the same architecture as the forward DWT. Finally, the area and the working frequency of the proposed architecture in 0.35um technology are 2.511x2.510 mm2, and 150 MHz, respectively.

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M3 - Conference article

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T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -

A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform

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