A Reed-Solomon Product-Code (RS-PC) decoder chip for DVD applications

Hsie-Chia Chang; C. B. Shung; Chen-Yi Lee

doi:10.1109/4.902763

A Reed-Solomon Product-Code (RS-PC) decoder chip for DVD applications

Hsie-Chia Chang^*, C. B. Shung, Chen-Yi Lee

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

51 Scopus citations

Abstract

In this paper, a Reed-Solomon Product-Code (RS-PC) decoder for DVD applications is presented. It mainly contains two frame-buffer controllers, a (182, 172) row RS decoder, and a (208, 192) column RS decoder. The RS decoder features an area-efficient key equation solver using a novel modified decomposed inversionless Berlekamp-Massey algorithm. The proposed RS-PC decoder solution was implemented using 0.6-μm CMOS single-poly double-metal (SPDM) standard cells. The chip size is 4.22 × 3.64 mm² with a core area of 2.90 × 2.88 mm², where the total gate count is about 26K. Test results show that the proposed RS-PC decoder chip can support 4 × DVD speed with off-chip frame buffers or 8 × DVD speed with embedded frame buffers operating at 3 V.

Original language	English
Pages (from-to)	229-238
Number of pages	10
Journal	IEEE Journal of Solid-State Circuits
Volume	36
Issue number	2
DOIs	https://doi.org/10.1109/4.902763
State	Published - Feb 2001

Keywords

DVD
Decomposed inversionless Berlekamp-Massey algorithm
Reed-Solomon Product-Code decoder

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10.1109/4.902763

Cite this

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title = "A Reed-Solomon Product-Code (RS-PC) decoder chip for DVD applications",

abstract = "In this paper, a Reed-Solomon Product-Code (RS-PC) decoder for DVD applications is presented. It mainly contains two frame-buffer controllers, a (182, 172) row RS decoder, and a (208, 192) column RS decoder. The RS decoder features an area-efficient key equation solver using a novel modified decomposed inversionless Berlekamp-Massey algorithm. The proposed RS-PC decoder solution was implemented using 0.6-μm CMOS single-poly double-metal (SPDM) standard cells. The chip size is 4.22 × 3.64 mm2 with a core area of 2.90 × 2.88 mm2, where the total gate count is about 26K. Test results show that the proposed RS-PC decoder chip can support 4 × DVD speed with off-chip frame buffers or 8 × DVD speed with embedded frame buffers operating at 3 V.",

keywords = "DVD, Decomposed inversionless Berlekamp-Massey algorithm, Reed-Solomon Product-Code decoder",

author = "Hsie-Chia Chang and Shung, {C. B.} and Chen-Yi Lee",

year = "2001",

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AU - Chang, Hsie-Chia

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AB - In this paper, a Reed-Solomon Product-Code (RS-PC) decoder for DVD applications is presented. It mainly contains two frame-buffer controllers, a (182, 172) row RS decoder, and a (208, 192) column RS decoder. The RS decoder features an area-efficient key equation solver using a novel modified decomposed inversionless Berlekamp-Massey algorithm. The proposed RS-PC decoder solution was implemented using 0.6-μm CMOS single-poly double-metal (SPDM) standard cells. The chip size is 4.22 × 3.64 mm2 with a core area of 2.90 × 2.88 mm2, where the total gate count is about 26K. Test results show that the proposed RS-PC decoder chip can support 4 × DVD speed with off-chip frame buffers or 8 × DVD speed with embedded frame buffers operating at 3 V.

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A Reed-Solomon Product-Code (RS-PC) decoder chip for DVD applications

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