A Reconfigurable In-SRAM Computing Architecture for DCNN Applications

Yu Hsien Lin, Chi Liu, Chia Lin Hu, Kang Yu Chang, Jia Yin Chen, Shyh Jye Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A methodology for Artificial Intelligence (AI) edge Deep Learning Neural Network (DNN) hardware design to increase the flexibility of each layer is emergent required. In order to support different DNN layers, a reconfigurable Universal Computation Element (UCE-R) is proposed. The UCE-R has its own controller and several UCE-Rs can be integrated to form a Reconfigurable UDNN (UDNN-R) engine for use in different kinds of AI edge applications. The design of UCE-R is implemented by using TSMC CMOS 28 um process. An UDNN-R is integrated for a Mobile-Net application.

Original languageEnglish
Title of host publication2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665419154
DOIs
StatePublished - 19 Apr 2021
Event2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Hsinchu, Taiwan
Duration: 19 Apr 202122 Apr 2021

Publication series

Name2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

Conference

Conference2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021
Country/TerritoryTaiwan
CityHsinchu
Period19/04/2122/04/21

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