@inproceedings{52350e89f05548428d58bf4856c814a3,
title = "A Reconfigurable In-SRAM Computing Architecture for DCNN Applications",
abstract = "A methodology for Artificial Intelligence (AI) edge Deep Learning Neural Network (DNN) hardware design to increase the flexibility of each layer is emergent required. In order to support different DNN layers, a reconfigurable Universal Computation Element (UCE-R) is proposed. The UCE-R has its own controller and several UCE-Rs can be integrated to form a Reconfigurable UDNN (UDNN-R) engine for use in different kinds of AI edge applications. The design of UCE-R is implemented by using TSMC CMOS 28 um process. An UDNN-R is integrated for a Mobile-Net application. ",
author = "Lin, {Yu Hsien} and Chi Liu and Hu, {Chia Lin} and Chang, {Kang Yu} and Chen, {Jia Yin} and Jou, {Shyh Jye}",
note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 ; Conference date: 19-04-2021 Through 22-04-2021",
year = "2021",
month = apr,
day = "19",
doi = "10.1109/VLSI-DAT52063.2021.9427349",
language = "English",
series = "2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings",
address = "美國",
}