A reconfigurable architecture for DSP system-on-chip

Lan-Rong Dung*, Yen Lin Lee, Chun Ming Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


Digital signal processing (DSP) has been moving into the era of system-on-chip (SoC) design. Yet, the development of SoC architectures is rather intellectual-property (IP)-based and presents several challenges to designers, notably in the transformation of algorithms and the integration of IP cores. Thus, this paper employs Petri nets to model the DSP algorithms and presents a novel architecture for rapid design of digital signal processing The architecture features a reconfigurable scheduler to dynamically schedule DSP operations onto processing elements and, thus, tolerates nondeterministic latencies of operations due to communication overhead and memory caching. Using the architecture, the designer can seamlessly plug in different IP cores to explore the alternative solutions and upgrade the architecture by reconfiguring the scheduler.

Original languageEnglish
Pages (from-to)109-113
Number of pages5
JournalCanadian Journal of Electrical and Computer Engineering
Issue number3-4
StatePublished - 1 Jul 2001


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