A quality scalable H.264/AVC baseline intra encoder for high definition video applications

Chun Hao Chang; Jia Wei Chen; Hsiu Cheng Chang; Yao Chang Yang; Jinn Shyan Wang; Jiun-In  Guo

doi:10.1109/SIPS.2007.4387602

A quality scalable H.264/AVC baseline intra encoder for high definition video applications

Chun Hao Chang^*, Jia Wei Chen, Hsiu Cheng Chang, Yao Chang Yang, Jinn Shyan Wang, Jiun-In Guo

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

In this paper, we propose a quality scalable H.264/AVC baseline intra encoder with two hardware sharing mechanisms and three timing optimizing schemes. The proposed hardware sharing schemes share the common terms among intra prediction of different modes to reduce the hardware cost. The proposed timing optimizing schemes are used to improve the data throughput rate. The proposed design supports different clock rates of 26/33/47 MHz and 70/85 MHz to encode SD and HD720 video sequences with 30fps respectively with different qualities. According to a 0.13μm CMOS technology, the proposed design costs 170K gates and 4.43 KB of internal SRAM at clock rate of 130MHz.

Original language	English
Title of host publication	2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings
Pages	521-526
Number of pages	6
DOIs	https://doi.org/10.1109/SIPS.2007.4387602
State	Published - 2007
Event	2007 IEEE Workshop on Signal Processing Systems, SiPS 2007 - Shanghai, China Duration: 17 Oct 2007 → 19 Oct 2007

Publication series

Name	IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)	1520-6130

Conference

Conference	2007 IEEE Workshop on Signal Processing Systems, SiPS 2007
Country/Territory	China
City	Shanghai
Period	17/10/07 → 19/10/07

Keywords

H.264/AVC
Intra encoder
Quality scalable

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10.1109/SIPS.2007.4387602

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Chang, C. H., Chen, J. W., Chang, H. C., Yang, Y. C., Wang, J. S., & Guo, J.-I. (2007). A quality scalable H.264/AVC baseline intra encoder for high definition video applications. In 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings (pp. 521-526). Article 4387602 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation). https://doi.org/10.1109/SIPS.2007.4387602

@inproceedings{5f2d9737dc7943df8f7816e5ec48eff6,

title = "A quality scalable H.264/AVC baseline intra encoder for high definition video applications",

abstract = "In this paper, we propose a quality scalable H.264/AVC baseline intra encoder with two hardware sharing mechanisms and three timing optimizing schemes. The proposed hardware sharing schemes share the common terms among intra prediction of different modes to reduce the hardware cost. The proposed timing optimizing schemes are used to improve the data throughput rate. The proposed design supports different clock rates of 26/33/47 MHz and 70/85 MHz to encode SD and HD720 video sequences with 30fps respectively with different qualities. According to a 0.13μm CMOS technology, the proposed design costs 170K gates and 4.43 KB of internal SRAM at clock rate of 130MHz.",

keywords = "H.264/AVC, Intra encoder, Quality scalable",

author = "Chang, {Chun Hao} and Chen, {Jia Wei} and Chang, {Hsiu Cheng} and Yang, {Yao Chang} and Wang, {Jinn Shyan} and Jiun-In Guo",

year = "2007",

doi = "10.1109/SIPS.2007.4387602",

language = "English",

isbn = "1424412226",

series = "IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation",

pages = "521--526",

booktitle = "2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings",

note = "2007 IEEE Workshop on Signal Processing Systems, SiPS 2007 ; Conference date: 17-10-2007 Through 19-10-2007",

}

Chang, CH, Chen, JW, Chang, HC, Yang, YC, Wang, JS & Guo, J-I 2007, A quality scalable H.264/AVC baseline intra encoder for high definition video applications. in 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings., 4387602, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, pp. 521-526, 2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Shanghai, China, 17/10/07. https://doi.org/10.1109/SIPS.2007.4387602

A quality scalable H.264/AVC baseline intra encoder for high definition video applications. / Chang, Chun Hao; Chen, Jia Wei; Chang, Hsiu Cheng et al.
2007 IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings. 2007. p. 521-526 4387602 (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, we propose a quality scalable H.264/AVC baseline intra encoder with two hardware sharing mechanisms and three timing optimizing schemes. The proposed hardware sharing schemes share the common terms among intra prediction of different modes to reduce the hardware cost. The proposed timing optimizing schemes are used to improve the data throughput rate. The proposed design supports different clock rates of 26/33/47 MHz and 70/85 MHz to encode SD and HD720 video sequences with 30fps respectively with different qualities. According to a 0.13μm CMOS technology, the proposed design costs 170K gates and 4.43 KB of internal SRAM at clock rate of 130MHz.

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A quality scalable H.264/AVC baseline intra encoder for high definition video applications

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