A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures

Jhin Bin Jiang; Kuen Cheng Chiang; Jyh-Jiun Shann

doi:10.1109/SIES.2012.6356604

A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures

Jhin Bin Jiang^*, Kuen Cheng Chiang, Jyh-Jiun Shann

^*Corresponding author for this work

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A coarse-grain reconfigurable architecture is an important technology for exploiting the parallelism of a program without compromise of the flexibility and has been adopted for high-performance embedded systems. However, the utilization of hardware resources may be limited by a large number of conditional executed operations. This paper represents a predicate-aware modulo scheduling which may map disjoint operations into the same processing element to reduce the requirements of hardware resources. Moreover, a weighted mapping decision algorithm has also been proposed to improve the execution performance for reconfigurable architecture. Our experimental results indicate that the initiation interval of a loop of the selected benchmarks may be reduced by 12% to 25.2% compared with a related work.

Original language	English
Title of host publication	7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings
Pages	311-314
Number of pages	4
DOIs	https://doi.org/10.1109/SIES.2012.6356604
State	Published - 2012
Event	7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Karlsruhe, Germany Duration: 20 Jun 2012 → 22 Jun 2012

Publication series

Name	7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings

Conference

Conference	7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012
Country/Territory	Germany
City	Karlsruhe
Period	20/06/12 → 22/06/12

Keywords

mode decision
modulo scheduling
predicated operation
reconfigurable architecture

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/SIES.2012.6356604

Cite this

Jiang, J. B., Chiang, K. C., & Shann, J.-J. (2012). A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures. In 7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings (pp. 311-314). Article 6356604 (7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings). https://doi.org/10.1109/SIES.2012.6356604

Jiang, Jhin Bin ; Chiang, Kuen Cheng ; Shann, Jyh-Jiun. / A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures. 7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings. 2012. pp. 311-314 (7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings).

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title = "A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures",

abstract = "A coarse-grain reconfigurable architecture is an important technology for exploiting the parallelism of a program without compromise of the flexibility and has been adopted for high-performance embedded systems. However, the utilization of hardware resources may be limited by a large number of conditional executed operations. This paper represents a predicate-aware modulo scheduling which may map disjoint operations into the same processing element to reduce the requirements of hardware resources. Moreover, a weighted mapping decision algorithm has also been proposed to improve the execution performance for reconfigurable architecture. Our experimental results indicate that the initiation interval of a loop of the selected benchmarks may be reduced by 12% to 25.2% compared with a related work.",

keywords = "mode decision, modulo scheduling, predicated operation, reconfigurable architecture",

author = "Jiang, {Jhin Bin} and Chiang, {Kuen Cheng} and Jyh-Jiun Shann",

year = "2012",

doi = "10.1109/SIES.2012.6356604",

language = "English",

isbn = "9781467326841",

series = "7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings",

pages = "311--314",

booktitle = "7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings",

note = "7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 ; Conference date: 20-06-2012 Through 22-06-2012",

}

Jiang, JB, Chiang, KC & Shann, J-J 2012, A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures. in 7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings., 6356604, 7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings, pp. 311-314, 7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012, Karlsruhe, Germany, 20/06/12. https://doi.org/10.1109/SIES.2012.6356604

A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures. / Jiang, Jhin Bin; Chiang, Kuen Cheng; Shann, Jyh-Jiun.
7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings. 2012. p. 311-314 6356604 (7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures

AU - Jiang, Jhin Bin

AU - Chiang, Kuen Cheng

AU - Shann, Jyh-Jiun

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Y1 - 2012

N2 - A coarse-grain reconfigurable architecture is an important technology for exploiting the parallelism of a program without compromise of the flexibility and has been adopted for high-performance embedded systems. However, the utilization of hardware resources may be limited by a large number of conditional executed operations. This paper represents a predicate-aware modulo scheduling which may map disjoint operations into the same processing element to reduce the requirements of hardware resources. Moreover, a weighted mapping decision algorithm has also been proposed to improve the execution performance for reconfigurable architecture. Our experimental results indicate that the initiation interval of a loop of the selected benchmarks may be reduced by 12% to 25.2% compared with a related work.

AB - A coarse-grain reconfigurable architecture is an important technology for exploiting the parallelism of a program without compromise of the flexibility and has been adopted for high-performance embedded systems. However, the utilization of hardware resources may be limited by a large number of conditional executed operations. This paper represents a predicate-aware modulo scheduling which may map disjoint operations into the same processing element to reduce the requirements of hardware resources. Moreover, a weighted mapping decision algorithm has also been proposed to improve the execution performance for reconfigurable architecture. Our experimental results indicate that the initiation interval of a loop of the selected benchmarks may be reduced by 12% to 25.2% compared with a related work.

KW - mode decision

KW - modulo scheduling

KW - predicated operation

KW - reconfigurable architecture

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U2 - 10.1109/SIES.2012.6356604

DO - 10.1109/SIES.2012.6356604

M3 - Conference contribution

AN - SCOPUS:84871565223

SN - 9781467326841

T3 - 7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings

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EP - 314

BT - 7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings

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Jiang JB, Chiang KC, Shann JJ. A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures. In 7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings. 2012. p. 311-314. 6356604. (7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings). doi: 10.1109/SIES.2012.6356604

A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures

Abstract

Publication series

Conference

Keywords

UN SDGs

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