A phase-based single-bit Delta-Sigma ADC architecture

Keyphrases

• Analog-to-digital Converter 100%
• Single-bit 100%
• Sigma-delta 100%
• Phase Coding 100%
• Delay-locked Loop 66%
• Charge Pump 33%
• Jitter 33%
• Feedback Path 33%
• Proposed Architecture 33%
• Signal Bandwidth 33%
• Delay-line-based 33%
• Voltage Controlled Delay Line 33%
• Quantization Noise Shaping 33%

Engineering

• Analog-to-Digital Converter 100%
• Single Bit 100%
• Locked Loop 66%
• Simulation Result 33%
• Charge Pump 33%
• Feedback Path 33%
• Electric Delay Lines 33%
• Quantization Noise 33%
• Quantizer 33%
• Bit Resolution 33%
• Signal Bandwidth 33%
• Loop Mechanism 33%