A phase-based single-bit Delta-Sigma ADC architecture

Yiqiao Lin; De Wen Liao; Chung-Chih Hung; Mohammed Ismail

doi:10.1109/NEWCAS.2011.5981256

A phase-based single-bit Delta-Sigma ADC architecture

Yiqiao Lin^*, De Wen Liao, Chung-Chih Hung, Mohammed Ismail

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A Phase-based Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) adopting a Delay-Locked-Loop (DLL) mechanism is presented. It is realized by a modification of a DLL using a Voltage-Controlled Delay Line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed δσ ADC achieved 7.99 bits resolution with OSR =32 for a 10 MHz signal bandwidth.

Original language	English
Title of host publication	2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
Pages	406-409
Number of pages	4
DOIs	https://doi.org/10.1109/NEWCAS.2011.5981256
State	Published - 13 Sep 2011
Event	2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011 - Bordeaux, France Duration: 26 Jun 2011 → 29 Jun 2011

Publication series

Name	2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011

Conference

Conference	2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011
Country/Territory	France
City	Bordeaux
Period	26/06/11 → 29/06/11

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10.1109/NEWCAS.2011.5981256

Cite this

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title = "A phase-based single-bit Delta-Sigma ADC architecture",

abstract = "A Phase-based Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) adopting a Delay-Locked-Loop (DLL) mechanism is presented. It is realized by a modification of a DLL using a Voltage-Controlled Delay Line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed δσ ADC achieved 7.99 bits resolution with OSR =32 for a 10 MHz signal bandwidth.",

author = "Yiqiao Lin and Liao, {De Wen} and Chung-Chih Hung and Mohammed Ismail",

year = "2011",

month = sep,

day = "13",

doi = "10.1109/NEWCAS.2011.5981256",

language = "English",

isbn = "9781612841359",

series = "2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011",

pages = "406--409",

booktitle = "2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011",

note = "2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011 ; Conference date: 26-06-2011 Through 29-06-2011",

}

Lin, Y, Liao, DW, Hung, C-C & Ismail, M 2011, A phase-based single-bit Delta-Sigma ADC architecture. in 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011., 5981256, 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011, pp. 406-409, 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011, Bordeaux, France, 26/06/11. https://doi.org/10.1109/NEWCAS.2011.5981256

A phase-based single-bit Delta-Sigma ADC architecture. / Lin, Yiqiao; Liao, De Wen; Hung, Chung-Chih et al.
2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011. 2011. p. 406-409 5981256 (2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ismail, Mohammed

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Y1 - 2011/9/13

N2 - A Phase-based Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) adopting a Delay-Locked-Loop (DLL) mechanism is presented. It is realized by a modification of a DLL using a Voltage-Controlled Delay Line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed δσ ADC achieved 7.99 bits resolution with OSR =32 for a 10 MHz signal bandwidth.

AB - A Phase-based Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) adopting a Delay-Locked-Loop (DLL) mechanism is presented. It is realized by a modification of a DLL using a Voltage-Controlled Delay Line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed δσ ADC achieved 7.99 bits resolution with OSR =32 for a 10 MHz signal bandwidth.

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SN - 9781612841359

T3 - 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011

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BT - 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011

T2 - 2011 IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011

Y2 - 26 June 2011 through 29 June 2011

ER -

A phase-based single-bit Delta-Sigma ADC architecture

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