A performance-aware IP core design for multi-mode transform coding using scalable-DA algorithm

Jia Wei Chen; Kuan Hung Chen; Jinn Shyan Wang; Jiun-In  Guo

doi:10.1109/ISCAS.2006.1692982

A performance-aware IP core design for multi-mode transform coding using scalable-DA algorithm

Jia Wei Chen^*, Kuan Hung Chen, Jinn Shyan Wang, Jiun-In Guo

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper proposes a performance-aware transform IP design which can be configured to appropriate hardware for different performance requirements on demand without requiring additional data bandwidth in Multi-mode video coding (JPEG/MPEG-1/2/4/H.261/H.263/H.264). Based on the scalable-DA approach, three schemes of hardware configurations which are respectively composed of 3, 6, and 12 data-paths are illustrated. The three schemes of the proposed performance-aware DCT/IDCT can achieve CIF, 720HD, and digital cinema video formats when operated at 9.13 MHz, 41.48 MHz, and 188.7S MHz, respectively.

Original language	English
Title of host publication	ISCAS 2006
Subtitle of host publication	2006 IEEE International Symposium on Circuits and Systems, Proceedings
Pages	1904-1907
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2006.1692982
State	Published - 2006
Event	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems - Kos, Greece Duration: 21 May 2006 → 24 May 2006

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Country/Territory	Greece
City	Kos
Period	21/05/06 → 24/05/06

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10.1109/ISCAS.2006.1692982

Cite this

Chen, J. W., Chen, K. H., Wang, J. S., & Guo, J.-I. (2006). A performance-aware IP core design for multi-mode transform coding using scalable-DA algorithm. In ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings (pp. 1904-1907). Article 1692982 (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2006.1692982

@inproceedings{7fdf9df9ace446b9ad7bf1ab934f011d,

title = "A performance-aware IP core design for multi-mode transform coding using scalable-DA algorithm",

abstract = "This paper proposes a performance-aware transform IP design which can be configured to appropriate hardware for different performance requirements on demand without requiring additional data bandwidth in Multi-mode video coding (JPEG/MPEG-1/2/4/H.261/H.263/H.264). Based on the scalable-DA approach, three schemes of hardware configurations which are respectively composed of 3, 6, and 12 data-paths are illustrated. The three schemes of the proposed performance-aware DCT/IDCT can achieve CIF, 720HD, and digital cinema video formats when operated at 9.13 MHz, 41.48 MHz, and 188.7S MHz, respectively.",

author = "Chen, {Jia Wei} and Chen, {Kuan Hung} and Wang, {Jinn Shyan} and Jiun-In Guo",

year = "2006",

doi = "10.1109/ISCAS.2006.1692982",

language = "English",

isbn = "0780393902",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1904--1907",

booktitle = "ISCAS 2006",

note = "ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems ; Conference date: 21-05-2006 Through 24-05-2006",

}

Chen, JW, Chen, KH, Wang, JS & Guo, J-I 2006, A performance-aware IP core design for multi-mode transform coding using scalable-DA algorithm. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1692982, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1904-1907, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 21/05/06. https://doi.org/10.1109/ISCAS.2006.1692982

A performance-aware IP core design for multi-mode transform coding using scalable-DA algorithm. / Chen, Jia Wei; Chen, Kuan Hung; Wang, Jinn Shyan et al.
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings. 2006. p. 1904-1907 1692982 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A performance-aware IP core design for multi-mode transform coding using scalable-DA algorithm

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AU - Chen, Kuan Hung

AU - Wang, Jinn Shyan

AU - Guo, Jiun-In

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N2 - This paper proposes a performance-aware transform IP design which can be configured to appropriate hardware for different performance requirements on demand without requiring additional data bandwidth in Multi-mode video coding (JPEG/MPEG-1/2/4/H.261/H.263/H.264). Based on the scalable-DA approach, three schemes of hardware configurations which are respectively composed of 3, 6, and 12 data-paths are illustrated. The three schemes of the proposed performance-aware DCT/IDCT can achieve CIF, 720HD, and digital cinema video formats when operated at 9.13 MHz, 41.48 MHz, and 188.7S MHz, respectively.

AB - This paper proposes a performance-aware transform IP design which can be configured to appropriate hardware for different performance requirements on demand without requiring additional data bandwidth in Multi-mode video coding (JPEG/MPEG-1/2/4/H.261/H.263/H.264). Based on the scalable-DA approach, three schemes of hardware configurations which are respectively composed of 3, 6, and 12 data-paths are illustrated. The three schemes of the proposed performance-aware DCT/IDCT can achieve CIF, 720HD, and digital cinema video formats when operated at 9.13 MHz, 41.48 MHz, and 188.7S MHz, respectively.

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DO - 10.1109/ISCAS.2006.1692982

M3 - Conference contribution

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SN - 0780393902

SN - 9780780393905

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1904

EP - 1907

BT - ISCAS 2006

T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems

Y2 - 21 May 2006 through 24 May 2006

ER -

A performance-aware IP core design for multi-mode transform coding using scalable-DA algorithm

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