A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT

Rei Chin Ju; Jia Wei Chen; Jiun-In  Guo; Tien-Fu Chen

doi:10.1109/ISCAS.2004.1329385

A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT

Rei Chin Ju^*, Jia Wei Chen, Jiun-In Guo, Tien-Fu Chen

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

This paper proposes a parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. For meeting different performance requirements, we provide a set of parameters in configuring the proposed IP generator including the types of DCT/IDCT architectures, the word-lengths of datapath, and the functions of transform. We adopt two different approaches in designing the 2-D DCT/IDCT including the high throughput adder-based approach and the low-cost group distributed arithmetic (GDA) approach, which exhibits different power dissipation and performance. In addition to generating the synthesizable VERILOG code and the associated supporting files for the IP core, the proposed power-aware IP generator can also perform the data precision analysis for users when trading-off the hardware cost, power consumption, and data precision in designing the DCT/IDCT IP for the portable multimedia applications.

Original language	English
Pages (from-to)	II769-II772
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
DOIs	https://doi.org/10.1109/ISCAS.2004.1329385
State	Published - 2004
Event	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada Duration: 23 May 2004 → 26 May 2004

Access to Document

10.1109/ISCAS.2004.1329385

Cite this

@article{b0254114e2d146f29d45061f90a3f773,

title = "A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT",

abstract = "This paper proposes a parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. For meeting different performance requirements, we provide a set of parameters in configuring the proposed IP generator including the types of DCT/IDCT architectures, the word-lengths of datapath, and the functions of transform. We adopt two different approaches in designing the 2-D DCT/IDCT including the high throughput adder-based approach and the low-cost group distributed arithmetic (GDA) approach, which exhibits different power dissipation and performance. In addition to generating the synthesizable VERILOG code and the associated supporting files for the IP core, the proposed power-aware IP generator can also perform the data precision analysis for users when trading-off the hardware cost, power consumption, and data precision in designing the DCT/IDCT IP for the portable multimedia applications.",

author = "Ju, {Rei Chin} and Chen, {Jia Wei} and Jiun-In Guo and Tien-Fu Chen",

year = "2004",

doi = "10.1109/ISCAS.2004.1329385",

language = "English",

volume = "2",

pages = "II769--II772",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2004 IEEE International Symposium on Cirquits and Systems - Proceedings ; Conference date: 23-05-2004 Through 26-05-2004",

}

TY - JOUR

T1 - A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT

AU - Ju, Rei Chin

AU - Chen, Jia Wei

AU - Guo, Jiun-In

AU - Chen, Tien-Fu

PY - 2004

Y1 - 2004

N2 - This paper proposes a parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. For meeting different performance requirements, we provide a set of parameters in configuring the proposed IP generator including the types of DCT/IDCT architectures, the word-lengths of datapath, and the functions of transform. We adopt two different approaches in designing the 2-D DCT/IDCT including the high throughput adder-based approach and the low-cost group distributed arithmetic (GDA) approach, which exhibits different power dissipation and performance. In addition to generating the synthesizable VERILOG code and the associated supporting files for the IP core, the proposed power-aware IP generator can also perform the data precision analysis for users when trading-off the hardware cost, power consumption, and data precision in designing the DCT/IDCT IP for the portable multimedia applications.

AB - This paper proposes a parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT. For meeting different performance requirements, we provide a set of parameters in configuring the proposed IP generator including the types of DCT/IDCT architectures, the word-lengths of datapath, and the functions of transform. We adopt two different approaches in designing the 2-D DCT/IDCT including the high throughput adder-based approach and the low-cost group distributed arithmetic (GDA) approach, which exhibits different power dissipation and performance. In addition to generating the synthesizable VERILOG code and the associated supporting files for the IP core, the proposed power-aware IP generator can also perform the data precision analysis for users when trading-off the hardware cost, power consumption, and data precision in designing the DCT/IDCT IP for the portable multimedia applications.

UR - http://www.scopus.com/inward/record.url?scp=4344570343&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2004.1329385

DO - 10.1109/ISCAS.2004.1329385

M3 - Conference article

AN - SCOPUS:4344570343

SN - 0271-4310

VL - 2

SP - II769-II772

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Cirquits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT

Abstract

Access to Document

Other files and links

Fingerprint

Cite this