A Parallel event-driven MOS timing simulator on distributed-memory multiprocessors

Wen Hsing Hsieh; Shyh-Jye Jou; Chau-Chin Su

doi:10.1109/ISCAS.1995.521578

A Parallel event-driven MOS timing simulator on distributed-memory multiprocessors

Wen Hsing Hsieh^*, Shyh-Jye Jou, Chau-Chin Su

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, PMOTA, a parallel event-driven relaxation-based algorithm for the timing simulation of MOS circuits, is proposed. Two new schemes, static data distribution and dynamic event assignment, are derived to reduce the communication overhead and achieve high speedup ratio, high processor utilization, and balanced load among processor elements. Implementation results show that parallel simulations on distributed memory multiprocessor are feasible for large scale circuit simulation.

Original language	English
Title of host publication	Proceedings of ISCAS'95 - International Symposium on Circuits and Systems
Pages	574-577
Number of pages	4
Volume	1
DOIs	https://doi.org/10.1109/ISCAS.1995.521578
State	Published - Apr 1995
Event	Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA Duration: 30 Apr 1995 → 3 May 1995

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISSN (Print)	0271-4310

Conference

Conference	Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3)
City	Seattle, WA, USA
Period	30/04/95 → 3/05/95

Access to Document

10.1109/ISCAS.1995.521578

Cite this

@inproceedings{85624a8a8901450389db4fd2d54215c9,

title = "A Parallel event-driven MOS timing simulator on distributed-memory multiprocessors",

abstract = "In this paper, PMOTA, a parallel event-driven relaxation-based algorithm for the timing simulation of MOS circuits, is proposed. Two new schemes, static data distribution and dynamic event assignment, are derived to reduce the communication overhead and achieve high speedup ratio, high processor utilization, and balanced load among processor elements. Implementation results show that parallel simulations on distributed memory multiprocessor are feasible for large scale circuit simulation.",

author = "Hsieh, {Wen Hsing} and Shyh-Jye Jou and Chau-Chin Su",

year = "1995",

month = apr,

doi = "10.1109/ISCAS.1995.521578",

language = "English",

volume = "1",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "574--577",

booktitle = "Proceedings of ISCAS'95 - International Symposium on Circuits and Systems",

note = "Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) ; Conference date: 30-04-1995 Through 03-05-1995",

}

Hsieh, WH, Jou, S-J & Su, C-C 1995, A Parallel event-driven MOS timing simulator on distributed-memory multiprocessors. in Proceedings of ISCAS'95 - International Symposium on Circuits and Systems. vol. 1, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 574-577, Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3), Seattle, WA, USA, 30/04/95. https://doi.org/10.1109/ISCAS.1995.521578

A Parallel event-driven MOS timing simulator on distributed-memory multiprocessors. / Hsieh, Wen Hsing; Jou, Shyh-Jye; Su, Chau-Chin.
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems. Vol. 1 1995. p. 574-577 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, PMOTA, a parallel event-driven relaxation-based algorithm for the timing simulation of MOS circuits, is proposed. Two new schemes, static data distribution and dynamic event assignment, are derived to reduce the communication overhead and achieve high speedup ratio, high processor utilization, and balanced load among processor elements. Implementation results show that parallel simulations on distributed memory multiprocessor are feasible for large scale circuit simulation.

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M3 - Conference contribution

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VL - 1

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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BT - Proceedings of ISCAS'95 - International Symposium on Circuits and Systems

T2 - Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3)

Y2 - 30 April 1995 through 3 May 1995

ER -

A Parallel event-driven MOS timing simulator on distributed-memory multiprocessors

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