@inproceedings{c3b7aabb844e49c29570bf90a8c3fe90,
title = "A Novel Technology Mapper for Complex Universal Gates",
abstract = "Complex universal logic gates, which may have higher density and flexibility than basic logic gates and look-up tables (LUT), are useful for cost-effective or security-oriented VLSI design requirements. However, most of the technology mapping algorithms aim to optimize combinational logic with basic standard cells or LUT components. It is desirable to investigate optimal technology mappers for complex universal gates in addition to basic standard cells and LUT components. This paper proposes a novel technology mapper for complex universal gates with a tight integration of the following techniques: Boolean network simulation with permutation classification, supergate library construction, dynamic programming based cut enumeration, Boolean matching with optimal universal cell covering. Experimental results show that the proposed method outperforms the state-of-the-art technology mapper in ABC, in terms of both area and delay.",
keywords = "complex universal gate, ECO, FPGA, Logic synthesis, structural ASIC, supergate library, technology mapping",
author = "Wu, {Meng Che} and Dao, {Ai Quoc} and Po-Hung Lin",
note = "Publisher Copyright: {\textcopyright} 2021 Association for Computing Machinery. Copyright: Copyright 2021 Elsevier B.V., All rights reserved.; 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 ; Conference date: 18-01-2021 Through 21-01-2021",
year = "2021",
month = jan,
day = "18",
doi = "10.1145/3394885.3431561",
language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "475--480",
booktitle = "Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021",
address = "美國",
}