A novel self-aligned T-shaped gate process for deep submicron Si MOSFET's fabrication

Horng-Chih Lin; Raymond Lin; Wen Fa Wu; Rong Ping Yang; Ming Shih Tsai; Tien-Sheng Chao; Tiao Yuan Huang

doi:10.1109/55.650343

A novel self-aligned T-shaped gate process for deep submicron Si MOSFET's fabrication

Horng-Chih Lin^*, Raymond Lin, Wen Fa Wu, Rong Ping Yang, Ming Shih Tsai, Tien-Sheng Chao, Tiao Yuan Huang

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

9 Scopus citations

Abstract

T-shaped gate electrode is highly desired for high-speed FET fabrication since it can significantly reduce the gate resistance. In this study, we propose and demonstrate a self-aligned method of forming T-shaped gate which is suitable for ULSI Si-MOSFET's fabrication. This method employs CMP planarization, BOE selective etching and poly-Si sidewall spacer techniques to form the T-shaped poly-Si gate structure. Ti and Co silicidation were also incorporated to demonstrate the effectiveness of this process. Our experimental results indicate that the proposed process not only reduces the parasitic gate resistance, but also improves the thermal stability of the gate structure.

Original language	English
Pages (from-to)	26-28
Number of pages	3
Journal	Ieee Electron Device Letters
Volume	19
Issue number	1
DOIs	https://doi.org/10.1109/55.650343
State	Published - Jan 1998

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abstract = "T-shaped gate electrode is highly desired for high-speed FET fabrication since it can significantly reduce the gate resistance. In this study, we propose and demonstrate a self-aligned method of forming T-shaped gate which is suitable for ULSI Si-MOSFET's fabrication. This method employs CMP planarization, BOE selective etching and poly-Si sidewall spacer techniques to form the T-shaped poly-Si gate structure. Ti and Co silicidation were also incorporated to demonstrate the effectiveness of this process. Our experimental results indicate that the proposed process not only reduces the parasitic gate resistance, but also improves the thermal stability of the gate structure.",

author = "Horng-Chih Lin and Raymond Lin and Wu, {Wen Fa} and Yang, {Rong Ping} and Tsai, {Ming Shih} and Tien-Sheng Chao and Huang, {Tiao Yuan}",

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AU - Lin, Horng-Chih

AU - Lin, Raymond

AU - Wu, Wen Fa

AU - Yang, Rong Ping

AU - Tsai, Ming Shih

AU - Chao, Tien-Sheng

AU - Huang, Tiao Yuan

PY - 1998/1

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N2 - T-shaped gate electrode is highly desired for high-speed FET fabrication since it can significantly reduce the gate resistance. In this study, we propose and demonstrate a self-aligned method of forming T-shaped gate which is suitable for ULSI Si-MOSFET's fabrication. This method employs CMP planarization, BOE selective etching and poly-Si sidewall spacer techniques to form the T-shaped poly-Si gate structure. Ti and Co silicidation were also incorporated to demonstrate the effectiveness of this process. Our experimental results indicate that the proposed process not only reduces the parasitic gate resistance, but also improves the thermal stability of the gate structure.

AB - T-shaped gate electrode is highly desired for high-speed FET fabrication since it can significantly reduce the gate resistance. In this study, we propose and demonstrate a self-aligned method of forming T-shaped gate which is suitable for ULSI Si-MOSFET's fabrication. This method employs CMP planarization, BOE selective etching and poly-Si sidewall spacer techniques to form the T-shaped poly-Si gate structure. Ti and Co silicidation were also incorporated to demonstrate the effectiveness of this process. Our experimental results indicate that the proposed process not only reduces the parasitic gate resistance, but also improves the thermal stability of the gate structure.

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A novel self-aligned T-shaped gate process for deep submicron Si MOSFET's fabrication

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