A novel programmable digital signal processor for multimedia applications

Li Chun Lin; Tay Jyi Lin; Chen Chia Lee; Chie Min Chao; Shin Kai Chen; Chia Hsien Liu; Pi Chen Hsiao; Chih-Wei Liu; Chein Wei Jen

doi:10.1109/APCCAS.2004.1412707

A novel programmable digital signal processor for multimedia applications

Li Chun Lin^*, Tay Jyi Lin, Chen Chia Lee, Chie Min Chao, Shin Kai Chen, Chia Hsien Liu, Pi Chen Hsiao, Chih-Wei Liu, Chein Wei Jen

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

This paper presents a novel DSP architecture for multimedia applications. The DSP core is a simple RISC processor from the programmer's view, which has a high-performance DSP unit and the applications can be easily targeted on the RISC shell to reduce the development time. Moreover, the DSP unit is itself a fully-programmable 4-way VLIW datapath, which has a novel ping-pong register file. To smooth the instruction execution of the two-level programmable DSP processor and improve the code density, we propose a hierarchical encoding scheme for variable-length instructions. The simulations show that our DSP has comparable performance with state-of-the-art DSP architectures, and the hierarchical instruction encoding saves 31%-64% code sizes compared to the fixed-length instruction encoding.

Original language	English
Pages	121-124
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2004.1412707
State	Published - Dec 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 6 Dec 2004 → 9 Dec 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan
City	Tainan
Period	6/12/04 → 9/12/04

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Lin, L. C., Lin, T. J., Lee, C. C., Chao, C. M., Chen, S. K., Liu, C. H., Hsiao, P. C., Liu, C.-W., & Jen, C. W. (2004). A novel programmable digital signal processor for multimedia applications. 121-124. Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan. https://doi.org/10.1109/APCCAS.2004.1412707

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title = "A novel programmable digital signal processor for multimedia applications",

abstract = "This paper presents a novel DSP architecture for multimedia applications. The DSP core is a simple RISC processor from the programmer's view, which has a high-performance DSP unit and the applications can be easily targeted on the RISC shell to reduce the development time. Moreover, the DSP unit is itself a fully-programmable 4-way VLIW datapath, which has a novel ping-pong register file. To smooth the instruction execution of the two-level programmable DSP processor and improve the code density, we propose a hierarchical encoding scheme for variable-length instructions. The simulations show that our DSP has comparable performance with state-of-the-art DSP architectures, and the hierarchical instruction encoding saves 31%-64% code sizes compared to the fixed-length instruction encoding.",

author = "Lin, {Li Chun} and Lin, {Tay Jyi} and Lee, {Chen Chia} and Chao, {Chie Min} and Chen, {Shin Kai} and Liu, {Chia Hsien} and Hsiao, {Pi Chen} and Chih-Wei Liu and Jen, {Chein Wei}",

year = "2004",

month = dec,

doi = "10.1109/APCCAS.2004.1412707",

language = "English",

pages = "121--124",

note = "2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology ; Conference date: 06-12-2004 Through 09-12-2004",

}

Lin, LC, Lin, TJ, Lee, CC, Chao, CM, Chen, SK, Liu, CH, Hsiao, PC, Liu, C-W & Jen, CW 2004, 'A novel programmable digital signal processor for multimedia applications', Paper presented at 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology, Tainan, Taiwan, 6/12/04 - 9/12/04 pp. 121-124. https://doi.org/10.1109/APCCAS.2004.1412707

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T1 - A novel programmable digital signal processor for multimedia applications

AU - Lin, Li Chun

AU - Lin, Tay Jyi

AU - Lee, Chen Chia

AU - Chao, Chie Min

AU - Chen, Shin Kai

AU - Liu, Chia Hsien

AU - Hsiao, Pi Chen

AU - Liu, Chih-Wei

AU - Jen, Chein Wei

PY - 2004/12

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AB - This paper presents a novel DSP architecture for multimedia applications. The DSP core is a simple RISC processor from the programmer's view, which has a high-performance DSP unit and the applications can be easily targeted on the RISC shell to reduce the development time. Moreover, the DSP unit is itself a fully-programmable 4-way VLIW datapath, which has a novel ping-pong register file. To smooth the instruction execution of the two-level programmable DSP processor and improve the code density, we propose a hierarchical encoding scheme for variable-length instructions. The simulations show that our DSP has comparable performance with state-of-the-art DSP architectures, and the hierarchical instruction encoding saves 31%-64% code sizes compared to the fixed-length instruction encoding.

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M3 - Paper

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T2 - 2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology

Y2 - 6 December 2004 through 9 December 2004

ER -

A novel programmable digital signal processor for multimedia applications

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