A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration

Shih Wei Lee; Shu Chiao Kuo; Kuan-Neng Chen

doi:10.1166/jnn.2018.14204

A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration

Shih Wei Lee, Shu Chiao Kuo, Kuan-Neng Chen

Research output: Contribution to journal › Article › peer-review

Abstract

A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.

Original language	American English
Pages (from-to)	1066-1069
Number of pages	4
Journal	Journal of Nanoscience and Nanotechnology
Volume	18
Issue number	2
DOIs	https://doi.org/10.1166/jnn.2018.14204
State	Published - Feb 2018

Keywords

Electrical Measurement
Misalignment
TSV 3D-IC
Three-dimensional (3D) integration

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10.1166/jnn.2018.14204

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title = "A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration",

abstract = "A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.",

keywords = "Electrical Measurement, Misalignment, TSV 3D-IC, Three-dimensional (3D) integration",

author = "Lee, {Shih Wei} and Kuo, {Shu Chiao} and Kuan-Neng Chen",

year = "2018",

month = feb,

doi = "10.1166/jnn.2018.14204",

language = "American English",

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journal = "Journal of Nanoscience and Nanotechnology",

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AU - Lee, Shih Wei

AU - Kuo, Shu Chiao

AU - Chen, Kuan-Neng

PY - 2018/2

Y1 - 2018/2

N2 - A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.

AB - A novel method for the inspection of the stacking misalignment in three-dimensional integration circuit (3DIC) by using electrical measurement is proposed. The metal line pattern designed in this paper combined with bump-less TSV fabrication process can successfully detect the direction and quantity of stacking fault. In addition, circuit combined with testing structure can be developed and simulated by using the current mirror concept and offered measurements with better efficiency.

KW - Electrical Measurement

KW - Misalignment

KW - TSV 3D-IC

KW - Three-dimensional (3D) integration

U2 - 10.1166/jnn.2018.14204

DO - 10.1166/jnn.2018.14204

M3 - Article

SN - 1533-4880

VL - 18

SP - 1066

EP - 1069

JO - Journal of Nanoscience and Nanotechnology

JF - Journal of Nanoscience and Nanotechnology

IS - 2

ER -

A Novel Method of Electrical Measurement for Stacking Error in 3D/2.5D Integration

Abstract

Keywords

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