A Novel Machine-Learning based SoC Performance Monitoring Methodology under Wide-Range PVT Variations with Unknown Critical Paths

Ding Hao Wang, Pei Ju Lin, Hui Ting Yang, Ching An Hsu, Sin Han Huang, Po-Hung Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Monitoring system-on-chip performance under process, voltage, and temperature (PVT) variations is very challenging, especially when the parasitic effects dominate the whole chip performance in advanced process nodes. Most of the previous works presented the performance monitoring methodologies based on known/predicted candidates of critical paths under different operating conditions. However, those methodologies may fail when the critical path is misrecognized or mispredicted. This paper proposes a novel machine-learning based chip performance monitoring methodology to accurately match the chip performance without requiring the information of critical paths under various PVT conditions. The experimental results based on measured chip performance show that the proposed methodology can achieve 98.5% accuracy in the worst case under wide-range PVT variations.

Original languageEnglish
Title of host publication2021 58th ACM/IEEE Design Automation Conference, DAC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1370-1371
Number of pages2
ISBN (Electronic)9781665432740
DOIs
StatePublished - 5 Dec 2021
Event58th ACM/IEEE Design Automation Conference, DAC 2021 - San Francisco, United States
Duration: 5 Dec 20219 Dec 2021

Publication series

NameProceedings - Design Automation Conference
Volume2021-December
ISSN (Print)0738-100X

Conference

Conference58th ACM/IEEE Design Automation Conference, DAC 2021
Country/TerritoryUnited States
CitySan Francisco
Period5/12/219/12/21

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