A Novel High Throughput-to-Area Efficiency and Strong-Resilience Datapath of AES for Lightweight Implementation in IoT Devices

Pao Ying Cheng, Ying Cheng Su, Paul C.P. Chao

Research output: Contribution to journalArticlepeer-review

Abstract

A new datapath for Advanced Encryption Standard (AES) is proposed in this work, which is successfully optimized with a high efficiency of throughout to area for lightweight applications in Internet of Things (IoT) devices. The proposed AES architecture enables parallel encryption of 32-bit blocks for efficient processing of 128-bit data while minimizing hardware area. Optimization is achieved by utilizing shift registers instead of conventional registers in the ShiftRows, MixColumns, and key expansion stages of the 32-bit AES operation. Our implementation, based on the TSMC 40 nm process, achieves a throughput of 692.65 Mb/s, with a gate count of 5.65K and a figure of merit (FOM) of 122.59 Mbps/k-gate, better than all the previous works in terms of efficiency. Furthermore, our proposed 32-bit datapath ensures security against correlation power analysis attacks owing to designed simultaneously active encryption and decryption, as the 32-bit key out of 128 bits remains unrevealed even with 100,000 traces for attack.

Original languageEnglish
Pages (from-to)1
Number of pages1
JournalIEEE Internet of Things Journal
DOIs
StateAccepted/In press - 2024

Keywords

  • 32-bit Datapath
  • Advanced Encryption Standard
  • Computer architecture
  • Differential Power Analysis
  • Encryption
  • Hardware
  • high efficiency
  • Internet of Things
  • lightweight
  • Logic gates
  • low area
  • Standards
  • Throughput

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