A novel glitch reduction circuitry for binary-weighted DAC

Keyphrases

• Circuitry 100%
• Digital-to-analog Converter 100%
• Binary Weights 100%
• Variable Delay 100%
• Delay Buffer 100%
• Glitch Power 100%
• Glitch Reduction 100%
• Power Supply 50%
• CMOS Technology 50%
• Proposed Design 50%
• 0.18-μm CMOS Technology 50%
• Low-power Design 50%
• Input Buffer 50%
• Spurious-free Dynamic Range 50%
• Current-steering Digital-to-analog Converter 50%
• Delay Difference 50%
• Low Glitch 50%

Engineering

• Digital-to-Analog Converter 100%
• Power Supply 33%
• Dynamic Range 33%
• Design Power 33%
• Input Buffer 33%
• Code Transition 33%
• Delay Difference 33%