A novel glitch reduction circuitry for binary-weighted DAC

Fang Ting Chou; Chia Min Chen; Zong Yi Chen; Chung-Chih Hung

doi:10.1109/APCCAS.2014.7032764

A novel glitch reduction circuitry for binary-weighted DAC

Fang Ting Chou, Chia Min Chen, Zong Yi Chen, Chung-Chih Hung

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm² core area, and dissipates 19mW from a single 1.8V power supply.

Original language	English
Title of host publication	2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	240-243
Number of pages	4
Edition	February
ISBN (Electronic)	9781479952304
DOIs	https://doi.org/10.1109/APCCAS.2014.7032764
State	Published - 5 Feb 2015
Event	2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan Duration: 17 Nov 2014 → 20 Nov 2014

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Number	February
Volume	2015-February

Conference

Conference	2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
Country/Territory	Japan
City	Ishigaki Island, Okinawa
Period	17/11/14 → 20/11/14

Keywords

Binary-weighted
DAC
variable-delay buffer

Access to Document

10.1109/APCCAS.2014.7032764

Cite this

Chou, F. T., Chen, C. M., Chen, Z. Y., & Hung, C.-C. (2015). A novel glitch reduction circuitry for binary-weighted DAC. In 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 (February ed., pp. 240-243). Article 7032764 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2015-February, No. February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2014.7032764

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abstract = "This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm2 core area, and dissipates 19mW from a single 1.8V power supply.",

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Chou, FT, Chen, CM, Chen, ZY & Hung, C-C 2015, A novel glitch reduction circuitry for binary-weighted DAC. in 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February edn, 7032764, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, no. February, vol. 2015-February, Institute of Electrical and Electronics Engineers Inc., pp. 240-243, 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki Island, Okinawa, Japan, 17/11/14. https://doi.org/10.1109/APCCAS.2014.7032764

A novel glitch reduction circuitry for binary-weighted DAC. / Chou, Fang Ting; Chen, Chia Min; Chen, Zong Yi et al.
2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 240-243 7032764 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 2015-February, No. February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents a high-speed, low-glitch, and low-power design for a 10-bit binary-weighted current-steering digital-to-analog converter (DAC). Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS technology, occupies 1.1mm2 core area, and dissipates 19mW from a single 1.8V power supply.

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Chou FT, Chen CM, Chen ZY, Hung CC. A novel glitch reduction circuitry for binary-weighted DAC. In 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014. February ed. Institute of Electrical and Electronics Engineers Inc. 2015. p. 240-243. 7032764. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; February). doi: 10.1109/APCCAS.2014.7032764

A novel glitch reduction circuitry for binary-weighted DAC

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