A novel clock recovering circuit is proposed and successfully validated by this study for a TRNG to thwart effectively all types of clock glitch attacks, including upward and downward clock glitches. It is known that true random number generators (TRNGs) act a crucial role in the cryptographic hardware of many edge devices such as sensors, while data are transmitted over the fly. The TRNG provides random numbers for ephemeral key exchange, key derivation function, and countermeasures against side-channel attack on sensors. The most efficient way to implement a random number generator is to sample the timing jitter from ring oscillators. The sampling clock generally comes from either an off-chip clock pin or the output from an internal phase-locked loop. However, both suffer from the threats of clock glitch injection attack. This study designs and validates successfully a novel clock recovering circuit in a digital ring-oscillator-based TRNG via field programmable gate array (FPGA). The clock recovering circuit is capable of recovering the glitch-injected clock to TRNG back to normal to thwart attacks. This designed circuit is composed of standard logic cells, being able to recover the clock from both upward clock glitch and downward clock glitch, with the resulting entropy restored to the originally expected level. With the property of synthesizable and low-cost, it is a favorable solution for IoT edge devices such as sensors to keep the quality of TRNG from the attack of clock glitch attacks.