TY - GEN
T1 - A new VLSI 2-D diagonal-symmetry filter architecture design
AU - Chen, Pei Yu
AU - Van, Lan-Da
AU - Reddy, Hari C.
AU - Lin, Chin-Teng
PY - 2008/12/1
Y1 - 2008/12/1
N2 - In this paper, we propose two new two-dimensional (2-D) IIR and FIR filter architectures for 2-D transfer function with diagonal symmetry. The presented type-I structure with diagonal symmetry has the lowest number of multipliers, and zero latency without sacrificing the number of the delay elements. Importantly, the proposed type-II IIR filter possesses high speed, local broadcast, and the same number of multipliers and latency as the type I shows at expense of a slight increment of number of delay elements.
AB - In this paper, we propose two new two-dimensional (2-D) IIR and FIR filter architectures for 2-D transfer function with diagonal symmetry. The presented type-I structure with diagonal symmetry has the lowest number of multipliers, and zero latency without sacrificing the number of the delay elements. Importantly, the proposed type-II IIR filter possesses high speed, local broadcast, and the same number of multipliers and latency as the type I shows at expense of a slight increment of number of delay elements.
UR - http://www.scopus.com/inward/record.url?scp=62949143191&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2008.4746024
DO - 10.1109/APCCAS.2008.4746024
M3 - Conference contribution
AN - SCOPUS:62949143191
SN - 9781424423422
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 320
EP - 323
BT - Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
PB - IEEE
T2 - APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Y2 - 30 November 2008 through 3 December 2008
ER -