A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

Chung-Yu Wu; Ming-Dou Ker; Chung Yuan Lee; Joe Ko; Larry Lin

doi:10.1109/CICC.1991.164085

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

Chung-Yu Wu^*, Ming-Dou Ker, Chung Yuan Lee, Joe Ko, Larry Lin

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structures is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown.

Original language	English
Title of host publication	Proceedings of the Custom Integrated Circuits Conference
Publisher	Publ by IEEE
ISBN (Print)	0780300157
DOIs	https://doi.org/10.1109/CICC.1991.164085
State	Published - 1 Dec 1991
Event	Proceedings of the IEEE 1991 Custom Integrated Circuits Conference - San Diego, CA, USA Duration: 12 May 1991 → 15 May 1991

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Conference

Conference	Proceedings of the IEEE 1991 Custom Integrated Circuits Conference
City	San Diego, CA, USA
Period	12/05/91 → 15/05/91

Access to Document

10.1109/CICC.1991.164085

Cite this

@inproceedings{4523f9fe8be94840b408911fbe8b4e1b,

title = "A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI",

abstract = "A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structures is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown.",

author = "Chung-Yu Wu and Ming-Dou Ker and Lee, {Chung Yuan} and Joe Ko and Larry Lin",

year = "1991",

month = dec,

day = "1",

doi = "10.1109/CICC.1991.164085",

language = "English",

isbn = "0780300157",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Publ by IEEE",

booktitle = "Proceedings of the Custom Integrated Circuits Conference",

note = "Proceedings of the IEEE 1991 Custom Integrated Circuits Conference ; Conference date: 12-05-1991 Through 15-05-1991",

}

Wu, C-Y, Ker, M-D, Lee, CY, Ko, J & Lin, L 1991, A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI. in Proceedings of the Custom Integrated Circuits Conference. Proceedings of the Custom Integrated Circuits Conference, Publ by IEEE, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, San Diego, CA, USA, 12/05/91. https://doi.org/10.1109/CICC.1991.164085

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI. / Wu, Chung-Yu; Ker, Ming-Dou; Lee, Chung Yuan et al.
Proceedings of the Custom Integrated Circuits Conference. Publ by IEEE, 1991. (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

AU - Wu, Chung-Yu

AU - Ker, Ming-Dou

AU - Lee, Chung Yuan

AU - Ko, Joe

AU - Lin, Larry

PY - 1991/12/1

Y1 - 1991/12/1

N2 - A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structures is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown.

AB - A novel CMOS on-chip ESD (electrostatic discharge) protection circuit which consists of dual parasitic SCR structures is proposed. Experimental results show that it can successfully provide for negative and positive ESD protection with failure thresholds greater than ±1 kV and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. Moreover, low triggering voltages in both SCRs can be readily achieved without involving device or junction breakdown.

UR - http://www.scopus.com/inward/record.url?scp=0026392746&partnerID=8YFLogxK

U2 - 10.1109/CICC.1991.164085

DO - 10.1109/CICC.1991.164085

M3 - Conference contribution

AN - SCOPUS:0026392746

SN - 0780300157

T3 - Proceedings of the Custom Integrated Circuits Conference

BT - Proceedings of the Custom Integrated Circuits Conference

PB - Publ by IEEE

T2 - Proceedings of the IEEE 1991 Custom Integrated Circuits Conference

Y2 - 12 May 1991 through 15 May 1991

ER -

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this