A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

Shih Hung Chen; Ming-Dou Ker; Che Hao Chuang

doi:10.1109/IPFA.2005.1469163

A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

Shih Hung Chen^*, Ming-Dou Ker, Che Hao Chuang

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

A new ESD failure mechanism has been found in the analog pins with pure-diode protection scheme during ND-mode ESD stress. The failure is caused by the parasitic npn interaction between ESD protection diode and guard ring structure. The parasitic npn bipolar, which was constructed between the N+/PW diode and the N+/NW guard ring, provides the discharging path between the I/O pad to the grounded VDD under the ND-mode ESD stress to cause a low ESD robustness of the analog I/O cell. The solution to overcome this ESD failure is also proposed.

Original language	English
Pages	209-212
Number of pages	4
DOIs	https://doi.org/10.1109/IPFA.2005.1469163
State	Published - Jun 2005
Event	12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005 - Singapore, Singapore Duration: 27 Jun 2005 → 1 Jul 2005

Conference

Conference	12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005
Country/Territory	Singapore
City	Singapore
Period	27/06/05 → 1/07/05

Access to Document

10.1109/IPFA.2005.1469163

Cite this

@conference{90dd53fb94f641a28cdd11dec76b1d75,

title = "A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology",

abstract = "A new ESD failure mechanism has been found in the analog pins with pure-diode protection scheme during ND-mode ESD stress. The failure is caused by the parasitic npn interaction between ESD protection diode and guard ring structure. The parasitic npn bipolar, which was constructed between the N+/PW diode and the N+/NW guard ring, provides the discharging path between the I/O pad to the grounded VDD under the ND-mode ESD stress to cause a low ESD robustness of the analog I/O cell. The solution to overcome this ESD failure is also proposed.",

author = "Chen, {Shih Hung} and Ming-Dou Ker and Chuang, {Che Hao}",

year = "2005",

month = jun,

doi = "10.1109/IPFA.2005.1469163",

language = "English",

pages = "209--212",

note = "12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005 ; Conference date: 27-06-2005 Through 01-07-2005",

}

A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology. / Chen, Shih Hung; Ker, Ming-Dou; Chuang, Che Hao.
2005. 209-212 Paper presented at 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005, Singapore, Singapore.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

AU - Chen, Shih Hung

AU - Ker, Ming-Dou

AU - Chuang, Che Hao

PY - 2005/6

Y1 - 2005/6

N2 - A new ESD failure mechanism has been found in the analog pins with pure-diode protection scheme during ND-mode ESD stress. The failure is caused by the parasitic npn interaction between ESD protection diode and guard ring structure. The parasitic npn bipolar, which was constructed between the N+/PW diode and the N+/NW guard ring, provides the discharging path between the I/O pad to the grounded VDD under the ND-mode ESD stress to cause a low ESD robustness of the analog I/O cell. The solution to overcome this ESD failure is also proposed.

AB - A new ESD failure mechanism has been found in the analog pins with pure-diode protection scheme during ND-mode ESD stress. The failure is caused by the parasitic npn interaction between ESD protection diode and guard ring structure. The parasitic npn bipolar, which was constructed between the N+/PW diode and the N+/NW guard ring, provides the discharging path between the I/O pad to the grounded VDD under the ND-mode ESD stress to cause a low ESD robustness of the analog I/O cell. The solution to overcome this ESD failure is also proposed.

UR - http://www.scopus.com/inward/record.url?scp=28044456482&partnerID=8YFLogxK

U2 - 10.1109/IPFA.2005.1469163

DO - 10.1109/IPFA.2005.1469163

M3 - Paper

AN - SCOPUS:28044456482

SP - 209

EP - 212

T2 - 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005

Y2 - 27 June 2005 through 1 July 2005

ER -

A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this