A new dynamic scaling FFT processor

Yu Wei Lin; Chen-Yi Lee

doi:10.1109/APCCAS.2004.1412793

A new dynamic scaling FFT processor

Yu Wei Lin^*, Chen-Yi Lee

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

Abstract

A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and prefetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 μm CMOS process with core area of 4.84mm² and consumes only 25.2 mW at 20 MHz.

Original language	English
Pages	449-452
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2004.1412793
State	Published - Dec 2004
Event	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology - Tainan, Taiwan Duration: 6 Dec 2004 → 9 Dec 2004

Conference

Conference	2004 IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS 2004: SoC Design for Ubiquitous Information Technology
Country/Territory	Taiwan
City	Tainan
Period	6/12/04 → 9/12/04

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10.1109/APCCAS.2004.1412793

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title = "A new dynamic scaling FFT processor",

abstract = "A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and prefetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 μm CMOS process with core area of 4.84mm2 and consumes only 25.2 mW at 20 MHz.",

author = "Lin, {Yu Wei} and Chen-Yi Lee",

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doi = "10.1109/APCCAS.2004.1412793",

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AB - A new FFT processor with radix-8 algorithm and novel matrix buffer is presented in this paper. About 64 K bit memory can be saved in 8 K-point FFT by new dynamic scaling approach. Moreover, with data scheduling and prefetched buffering, single-port memory can be adopted in our FFT processor. A test chip for 8 K mode DVB-T system has been designed and fabricated using 0.18 μm CMOS process with core area of 4.84mm2 and consumes only 25.2 mW at 20 MHz.

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A new dynamic scaling FFT processor

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