Abstract
In this paper, we propose a new two-dimensional (2-D) systolic-array digital filter using locally broadcast scheme that is the hybrid of a modified reordering and another systolic transformation. This architecture occupies locally broadcast, lower quantization error and zero latency without sacrificing the number of multipliers as well as delay elements under the accepted critical period. In addition, the widely used 2-D cascaded systolic digital filter can be described and reconstructed by similar methodology.
Original language | English |
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Pages | 579-582 |
Number of pages | 4 |
DOIs | |
State | Published - 2000 |
Event | 2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin, China Duration: 4 Dec 2000 → 6 Dec 2000 |
Conference
Conference | 2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems |
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Country/Territory | China |
City | Tianjin |
Period | 4/12/00 → 6/12/00 |