A Multi-Step Incremental Analog-to-Digital Converter with a Single Opamp and Two- Capacitor SAR Extended Counting

Shih Che Kuo, Jia Sheng Huang, Yu Cheng Huang, Chia Wei Kao, Che Wei Hsu, Chia Hung Chen*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This work describes a hybrid incremental ADC (IADC) with two-capacitor (2-C) successive-approximation registers (SAR) extended counting in two-step operation to achieve high resolution data conversion. The circuits in the first step is acting as a first-order incremental analog-to-digital converter (IADC). Finite impulse response (FIR) DAC is incorporated in the loop filter to reduce the transient voltage step. It is reconfigured as a 2-C SAR to perform extended counting technique in the second step. Only one opamp is re-used in both steps. The hardware is prototyped in 0.18~mu textm CMOS technology, and the hybrid ADC accomplishes a measured DR / SNR / SNDR of 100.2 / 97.1 / 96.6 dB and an input signal bandwidth of 1.2 kHz. Operated at 1.5-V, it consumes 33.2~mu textW , and this achieves a Walden figure-of-merit (FoM) of 0.25 pJ/conversion-step and Schreier FoM of 175.8 dB.

Original languageEnglish
Article number9431347
Pages (from-to)2890-2899
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume68
Issue number7
DOIs
StatePublished - Jul 2021

Keywords

  • analog-to-digital converter (ADC)
  • binary search
  • Delta sigma (ΔΣ) modulator
  • extended counting
  • FIR DAC
  • incremental data converters
  • infinite impulse response
  • measurement and instrumentation
  • multi-stage noise shaping (MASH)
  • multi-step
  • multi-step incremental ADC
  • sensor interface
  • successive approximation register (SAR)
  • time-domain analysis
  • two step
  • two-capacitor

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