A Multi-phase Series-Parallel with Bond Wire Auxiliary Fully-Integrated 250pF Switched-Capacitor with 13.6mV output ripple for Supplying Temperature Sensor with 0.1°C Accuracy to Early Detect COVID-19

Shu Yung Lin, Chin Hsiang Liang, Kai Syun Chang, Ke Horng Chen, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Temperature sensing is an important means for the early detection of COVID-19 infection. Thus, it is important to supply a 0.95V(\pm 0.5\%) to the wearable temperature sensor (top left in Fig. 1) by a fully integrated switched-capacitor (SC) converter with small on-chip capacitors CFLY and COUT. For small chip area, the value of CTOT (=CFLY+COUT, where CFLY and COUT are flying capacitor and output capacitor, respectively) needs to be less than 250pF to ensure the temperature sensor is small enough. The required temperature detection accuracy of 0.1°C limits the output voltage ripple ΔVOUT of the SC to less than 15mV, where ΔVOUT is inversely proportional to the switching frequency FCLK and COUT. If CTOT <250pF and ΔVOUT< 15mV, then FCLK is tens of GHz. In [1], a digital 2-/3-Phase SC is used to decrease ΔVOUT and to improve efficiency, but the required off-chip capacitor is not suitable for wearable devices. In [2], an SC Resistance low-dropout (SCR-DLDO) regulator uses a small on-chip capacitor of 0.365nF, but FCLK of 1.55GHz causes a larger switching loss. In [3], since FCLK is determined by (LC)1/2=47.5MHz, the large on-chip inductor will cause higher conduction power loss due to its worse quality factor. Moreover, a pulse skipping technique is required to decrease FCLK and enhance light-load efficiency at the cost of large ΔVOUT. Although [4] attempts to have many voltage conversion ratios (VCR) to maintain high efficiency, there are still problems with reduced drive capability and reduced efficiency on some VCRs. In [5], switching frequency can be reduced to 95 MHz, using a capacitor-dithering method with 41 interleaved phases. However, the peak efficiency degrades to 70.8% due to the charge sharing loss from the 41 interleaving cells.

Original languageEnglish
Title of host publicationProceedings - A-SSCC 2021
Subtitle of host publicationIEEE Asian Solid-State Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665443500
DOIs
StatePublished - 2021
Event2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021 - Busan, Korea, Republic of
Duration: 7 Nov 202110 Nov 2021

Publication series

NameProceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference

Conference

Conference2021 IEEE Asian Solid-State Circuits Conference, A-SSCC 2021
Country/TerritoryKorea, Republic of
CityBusan
Period7/11/2110/11/21

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